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公开(公告)号：US3983500A
公开(公告)日：1976-09-28
申请号：US502531
申请日：1974-09-03
申请人： Nobuaki Takahashi , Kazunori Nishikawa , Yoshiki Iwasaki , Masaaki Satoh , Katsuhiro Ohba , Shinji Nakamura , Tatsuo Sawada , Nobuhide Ohsaki , Yasuo Itoh , Nobuaki Suda , Yasuhisa Okabe , Hideaki Ozaki
发明人： Nobuaki Takahashi , Kazunori Nishikawa , Yoshiki Iwasaki , Masaaki Satoh , Katsuhiro Ohba , Shinji Nakamura , Tatsuo Sawada , Nobuhide Ohsaki , Yasuo Itoh , Nobuaki Suda , Yasuhisa Okabe , Hideaki Ozaki
CPC分类号： H03D3/244 , G11B20/00992 , G11B23/0007 , H04S3/006
摘要： An angle modulated wave demodulation system demodulates an input angle modulated wave by means of a phase locked loop system which comprises a phase comparator, which is operated responsive to an input angle modulated wave. A voltage controlled oscillator is supplied with a part of the output of the phase comparator which controls its oscillation frequency. The oscillator supplies its oscillation frequency to the phase comparator. The phase locked loop system has a lock frequency range which decreases its width when the level of the input angle modulated wave is below a predetermined level. The portion of this lock range in which the width of the lock range decreases is positively utilized. The voltage controlled oscillator oscillates at a frequency equal to the center frequency of the carrier of the input angle modulated wave, when the phase locked loop becomes unlocked.
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公开(公告)号：US4107478A
公开(公告)日：1978-08-15
申请号：US698191
申请日：1976-06-21
申请人： Nobuaki Takahashi , Kazunori Nishikawa , Yoshiki Iwasaki , Masaaki Satoh , Katsuhiro Ohba , Shinji Nakamura , Tatsuo Sawada , Nobuhide Ohsaki , Yasuo Itoh , Nobuaki Suda , Yasuhisa Okabe , Hideaki Ozaki
发明人： Nobuaki Takahashi , Kazunori Nishikawa , Yoshiki Iwasaki , Masaaki Satoh , Katsuhiro Ohba , Shinji Nakamura , Tatsuo Sawada , Nobuhide Ohsaki , Yasuo Itoh , Nobuaki Suda , Yasuhisa Okabe , Hideaki Ozaki
CPC分类号： H03D3/244 , G11B20/00992 , G11B23/0007 , H04S3/006
摘要： An angle modulated wave demodulation system demodulates an input angle modulated wave by means of a phase locked loop system which comprises a phase comparator, which is operated responsive to an input angle modulated wave. A voltage controlled oscillator is supplied with a part of the output of the phase comparator which controls its oscillation frequency. The oscillator supplies its oscillation frequency to the phase comparator. The phase locked loop system has a lock frequency range which decreases its width when the level of the input angle modulated wave is below a predetermined level. The portion of this lock range in which the width of the lock range decreases is positively utilized. The voltage controlled oscillator oscillates at a frequency equal to the center frequency of the carrier of the input angle modulated wave, when the phase locked loop becomes unlocked.
摘要翻译： 角度调制波解调系统通过锁相环系统对输入角调制波进行解调，该锁相环系统包括响应于输入角调制波操作的相位比较器。 电压控制振荡器被提供有控制其振荡频率的相位比较器的输出的一部分。 振荡器将其振荡频率提供给相位比较器。 锁相环系统具有当输入角度调制波的电平低于预定电平时减小其宽度的锁定频率范围。 正确地利用锁定范围的宽度减小的锁定范围的部分。 当锁相环解锁时，压控振荡器的振荡频率等于输入角调制波的载波的中心频率。
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公开(公告)号：US4516163A
公开(公告)日：1985-05-07
申请号：US508540
申请日：1983-06-28
CPC分类号： G11B20/1809 , G11B20/10 , G11B20/10527
摘要： A digital information recording system comprises a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, a detector for successively detecting values of each of a predetermined number of words from each of the digital information signals of a plurality of channels in the randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in the one word are all "1" or all "0", a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of the digital information signals of a plurality of channels, a polarity inverting circuit for passing the randomized digital signal unchanged during a period in which the detection signal is not generated from the detector, and inverting the polarity of the least significant bit in one word from each of the digital information signals of a plurality of channels in the randomized digital signal when simultaneously applied with the detection signal and the timing signal, and a recording circuit for recording a digital signal obtained from the polarity inverting circuit.
摘要翻译： 数字信息记录系统包括一个随机数字信号形成电路，用于通过对数字信号中的至少数个信道信号和独立产生的随机码序列至少进行模2加法来形成随机数字信号， 一个检测器，用于根据一个字连续地检测随机数字信号中的多个通道的每个数字信息信号中的每一个的预定数量的字的值，并且仅当在一个字中的位的值时产生检测信号 一个字全部为“1”或全部为“0”，定时电路用于在与多个通道的每个数字信息信号中的一个字中的最低有效位的发送周期相对应的每个周期产生定时信号， 极性反转电路，用于在不从d产生检测信号的期间内使随机数字信号不变 并且当同时施加检测信号和定时信号时，将随机数字信号中的多个通道的数字信息信号中的每一个的一个字中的最低有效位的极性反转，以及记录电路 从极性反转电路获得的数字信号。
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公开(公告)号：US4561083A
公开(公告)日：1985-12-24
申请号：US496589
申请日：1983-05-20
申请人： Kazunori Nishikawa , Yoshiki Iwasaki , Isao Masuda , Shoji Ueno , Makoto Komura , Nobuaki Takahashi
发明人： Kazunori Nishikawa , Yoshiki Iwasaki , Isao Masuda , Shoji Ueno , Makoto Komura , Nobuaki Takahashi
CPC分类号： H04N5/956
摘要： A memory circuit write-in system comprises a first circuit for supplying a digital signal including a time base fluctuation component, where one frame of the digital signal is constituted by at least a synchronizing signal and information data and the digital signal has a first repetition frequency with a period of one frame of the digital signal, a memory circuit for writing therein and reading out therefrom the digital signal supplied from the first circuit, and a second circuit for applying a write-in control signal to the memory circuit. The write-in control signal includes no time base fluctuation component and has a second repetition frequency substantially equal to the first repetition frequency, and the memory circuit is controlled by the write-in control signal so that write-in of the digital signal is carried out with a write-in period in a range of two times within the one frame period.
摘要翻译： 存储电路写入系统包括：第一电路，用于提供包括时基波动分量的数字信号，其中数字信号的一帧至少由同步信号和信息数据构成，数字信号具有第一重复频率 具有数字信号的一帧的周期，用于在其中写入并从其读出从第一电路提供的数字信号的存储器电路，以及用于将写入控制信号施加到存储器电路的第二电路。 写入控制信号不包括时基波动分量，并且具有基本上等于第一重复频率的第二重复频率，并且存储电路由写入控制信号控制，以便承载数字信号的写入 在一个帧周期内以两次的写入周期输出。
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公开(公告)号：US3934087A
公开(公告)日：1976-01-20
申请号：US403635
申请日：1973-10-04
申请人： Nobuaki Takahashi , Yoshiki Iwasaki , Masao Kasuga , Yasuo Itoh
发明人： Nobuaki Takahashi , Yoshiki Iwasaki , Masao Kasuga , Yasuo Itoh
摘要： A system for demodulating angle modulated waves comprises a phase locked loop including a phase comparator and a voltage controlled oscillator. An attenuation means is inserted into the phase locked loop. This attenuation means does not affect the DC component of an input angle modulated wave, but does cause an attenuation with respect to an AC component, to cause a decrease in the loop gain. The phase locked loop has a DC lock range exhibiting a relatively wide lock range width even when the input level is relatively low and an AC lock range produced by the attenuation circuit and exhibiting a relatively narrow lock range width when the input level is relatively low. The attenuation means detects an abnormality in the angle modulated wave, the harmonics component of the direct wave, and the like. A variable attenuation circuit controlled by the output of the detecting means is varied in its attenuation quantity.
摘要翻译： 用于解调角度调制波的系统包括包括相位比较器和压控振荡器的锁相环。 衰减装置插入到锁相环中。 该衰减装置不影响输入角调制波的直流分量，但是相对于AC分量产生衰减，导致环路增益的降低。 即使当输入电平相对较低时，锁相环也具有相对宽的锁定范围宽度的DC锁定范围，并且当输入电平相对较低时，锁相环由衰减电路产生并产生相对窄的锁定范围宽度。 衰减装置检测角度调制波的异常，直接波的谐波分量等。 由检测装置的输出控制的可变衰减电路的衰减量变化。
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公开(公告)号：US4667318A
公开(公告)日：1987-05-19
申请号：US543402
申请日：1983-10-19
CPC分类号： G11B20/10527 , G11B20/1809 , G11B27/105 , G11B27/3027 , G11B27/3036 , G11B27/34 , H04N1/2166 , G11B2220/20
摘要： A data producing device in a signal reproducing apparatus, comprises a shift register supplied with synchronizing signals and codes which are time-sequentially reproduced from a recording medium, synchronizing signal detectors supplied with the synchronizing signals from the shift register, data transfer circuits provided in parallel with respect to each other and in series with the synchronizing signal detectors, and a control circuit for controlling the data transfer circuits so that a data is selectively read out and produced from a desired data transfer circuit among the plurality of data transfer circuits. The reproduced synchronizing signals and codes are transferred to the shift register and are read out from the shift register in response to a clock pulse having a predetermined frequency. The number of the synchronizing signal detectors is equal to the number of kinds of the synchronizing signals, and the synchronizing signal detectors are provided in parallel with respect to each other. Each of the synchronizing signal detectors detect a specific synchronizing signal. A data in a predetermined code among the codes supplied to the data transfer circuits is transferred to the data transfer circuits, when a synchronizing signal for discriminating the predetermined code is detected in the synchronizing signal detectors and supplied to the data transfer circuits.
摘要翻译： 信号再现装置中的数据产生装置包括：移位寄存器，其提供有从记录介质被时间顺序再现的同步信号和代码，提供有来自移位寄存器的同步信号的同步信号检测器，并行提供的数据传送电路 并且与同步信号检测器串联的控制电路，以及用于控制数据传送电路的控制电路，使得从多个数据传送电路中的期望的数据传送电路选择性地读出和产生数据。 再现的同步信号和代码被传送到移位寄存器，并且响应于具有预定频率的时钟脉冲从移位寄存器读出。 同步信号检测器的数量等于同步信号的种类数，并且同步信号检测器相对于彼此并联设置。 每个同步信号检测器检测特定的同步信号。 当在同步信号检测器中检测到用于识别预定码的同步信号并提供给数据传送电路时，提供给数据传送电路的代码中的预定代码中的数据被传送到数据传送电路。
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7.发明授权Synchronizing signal detecting circuit in a digital signal transmitting system 失效在数字信号发送系统中同步信号检测电路
公开(公告)号：US4596981A
公开(公告)日：1986-06-24
申请号：US615237
申请日：1984-05-29
申请人： Shoji Ueno , Kazunori Nishikawa , Yoshiki Iwasaki , Isao Masuda , Makoto Komura
发明人： Shoji Ueno , Kazunori Nishikawa , Yoshiki Iwasaki , Isao Masuda , Makoto Komura
摘要： A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of the synchronizing signal by a predetermined number of bits. The synchronizing signal detecting circuit comprises a counter which is reset when a synchronizing signal detection output which has been discriminated as being correct by use of the error checking code is continuously obtained for N times, where N is a natural number greater than or equal to two.
摘要翻译： 在数字信号发送系统中使用同步信号检测电路，该数字信号发送系统发送数字信号，其中信号以块为单位进行时间顺序复用，其中每个块由作为经受数字信号的信息信号的数字数据组成 调制，具有固定模式的同步信号和布置在与同步信号的位置分离预定位数的位置处的错误校验码。 同步信号检测电路包括一个计数器，当通过使用错误校验码被鉴别为正确的同步信号检测输出连续获得N次时，复位，其中N是大于或等于2的自然数 。
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8.发明授权Circuit arrangement for a disk player for reproducing information prerecorded in the form of pits 失效用于再现以凹坑形式预先记录的信息的盘播放器的电路装置
公开(公告)号：US4509155A
公开(公告)日：1985-04-02
申请号：US383258
申请日：1982-05-28
CPC分类号： G11B20/10009
摘要： In a circuit arrangement for a disk player of the type arranged to reproduce information prerecorded in the form of pits, a variable gain circuit for changing the frequency characteristic of the reproduced signal is provided. The level of the reproduced signal is detected at high and low frequencies so as to produce a control signal the voltage of which varies in accordance with the difference between the level of the high frequency signal component and the level of the low frequency component. The control signal is then applied to the variable gain circuit receiving the reproduced signal so that the frequency characteristic of the reproduced signal will be controlled. Thus, the level of the reproduced signal is boosted at its high frequency range.
摘要翻译： 在用于再现以凹坑形式预先记录的信息的类型的盘播放器的电路装置中，提供了用于改变再现信号的频率特性的可变增益电路。 在高频和低频处检测再现信号的电平，以产生其电压根据高频信号分量的电平与低频分量的电平之间的差而变化的控制信号。 然后，控制信号被施加到接收再现信号的可变增益电路，从而控制再生信号的频率特性。 因此，再现信号的电平在其高频范围被提升。
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公开(公告)号：US4186281A
公开(公告)日：1980-01-29
申请号：US843863
申请日：1977-10-20
申请人： Masao Kasuga , Nobuaki Takahashi , Fujio Suzuki , Yoshiki Iwasaki
发明人： Masao Kasuga , Nobuaki Takahashi , Fujio Suzuki , Yoshiki Iwasaki
CPC分类号： H04S3/006
摘要： A multichannel record disc reproducing apparatus comprises a first phase locked loop circuit including a phase comparator and a voltage controlled oscillator for demodulating an angle-modulated wave signal. The modulated signal is separated from a composite signal picked up from a multichannel record disc on which a multiplexed direct wave signal and an angle-modulated wave signal are recorded. The output of the first phase locked loop is a demodulated signal. A second phase locked loop circuit includes a phase comparator and a voltage controlled oscillator, supplied with the separated angle-modulated wave signal and having a lock range of a width which covers and is wider than the maximum lock range width of the first phase locked loop circuit. A synchronous detector compares the phases of the angle-modulated wave signal and the output signal of voltage controlled oscillator of the second phase locked loop. The synchronous detector operates when the phase difference of the two signals deviates sufficiently from a predetermined phase difference. Means are provided for reducing or removing noise components which are developed in the demodulated signal in accordance with the output of the synchronous detector. This noise reduction or removal is provided in the first phase locked loop circuit and/or in a channel for transmitting the demodulated signal.
摘要翻译： 多通道记录盘重放装置包括第一锁相环电路，其包括用于解调角度调制波信号的相位比较器和压控振荡器。 调制信号与从其上记录有多路复用直接波信号和角度调制波信号的多通道记录盘拾取的复合信号分离。 第一锁相环的输出是解调信号。 第二锁相环电路包括相位比较器和压控振荡器，被提供有分离的角度调制波信号并且具有覆盖并且比第一锁相环的最大锁定范围宽度宽的宽度的锁定范围 电路。 同步检波器将角度调制波信号的相位与第二锁相环的压控振荡器的输出信号进行比较。 当两个信号的相位差从预定的相位差充分偏离时，同步检测器工作。 提供了用于根据同步检测器的输出减少或去除在解调信号中产生的噪声分量的装置。 在第一锁相环电路和/或用于发送解调信号的信道中提供该噪声降低或去除。
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公开(公告)号：US4008381A
公开(公告)日：1977-02-15
申请号：US610463
申请日：1975-09-04
申请人： Nobuaki Takahashi , Takaro Mori , Yoshiki Iwasaki
发明人： Nobuaki Takahashi , Takaro Mori , Yoshiki Iwasaki
IPC分类号： G11B3/00
CPC分类号： G11B3/00
摘要： A multichannel record disc recording system comprises: a circuit for shaping sum and difference signals from multichannel signals, angle modulating the difference signal, multiplexing the sum signal and the angle-modulated difference signal, and recording the resulting signal on a record disc. A first level control circuit, in the transmission system for the sum signal, operates to attenuate the high-frequency band of components of the sum signal when its level is at a high level. A second level control circuit, in the transmission system of the difference signal, operates to attenuate the middle-high frequency band of components of the difference signal when its level is at a high level. The first level control circuit attenuates the level of the sum signal to prevent an admixing of the higher harmonics of the high frequency component of the sum signal into the band of the angle-modulated difference signal. The second level control circuit attenuates the level of the difference signal to prevent an overdeviation due to overmodulation of the angle-modulated difference signal.
摘要翻译： 多通道记录盘记录系统包括：用于对来自多通道信号的和和信号进行整形的电路，对差分信号进行角度调制，对和信号和角度调制的差分信号进行多路复用，并将得到的信号记录在记录盘上。 在和信号的传输系统中的第一电平控制电路在其电平处于高电平时衰减和信号的分量的高频带。 差分信号的传输系统中的第二电平控制电路在其电平处于高电平时，对差分信号的分量的中高频带进行衰减。 第一电平控制电路衰减和信号的电平，以防止将和信号的高频分量的高次谐波混入角度调制差分信号的频带中。 第二电平控制电路衰减差分信号的电平，以防止由角度调制差分信号的过调制引起的过度偏移。
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