公开(公告)号：US06807124B2

公开(公告)日：2004-10-19

申请号：US10347434

申请日：2003-01-21

申请人： Nobuhiro Tsuda ,  Koji Nii ,  Shoji Okuda

发明人： Nobuhiro Tsuda ,  Koji Nii ,  Shoji Okuda

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A memory device that consumes no wasteful power in selecting memory cells and achieves high operating speed and size and cost reductions, is provided. In reading of memory cell information, only a single memory cell in a single local block is activated through a read word line. Specifically, AND circuits are provided in correspondence with all memory cells. Each AND circuit receives as its inputs a block select signal for selecting one of the local blocks and an in-block memory cell select signal for selecting one of the memory cells in each local block in a common manner among the local blocks. The outputs from the AND circuits are applied to read word lines. Unselected memory cells are not activated and therefore no current flows from those memory cells to local read bit lines, thereby preventing wasteful power consumption.

摘要翻译： 提供了在选择存储器单元中消耗浪费电力并实现高操作速度和尺寸和成本降低的存储器件。 在读取存储单元信息时，通过读字线仅激活单个本地块中的单个存储单元。 具体地，与所有存储单元相对应地提供AND电路。 每个AND电路接收用于选择本地块之一的块选择信号和块内存储单元选择信号，用于以局部块中的共同方式选择每个本地块中的一个存储单元。 来自“与”电路的输出被应用于读取字线。 未选择的存储单元不被激活，因此没有电流从这些存储器单元流到本地读取位线，从而防止浪费的功耗。

公开(公告)号：US06535417B2

公开(公告)日：2003-03-18

申请号：US09837233

申请日：2001-04-19

申请人： Nobuhiro Tsuda ,  Koji Nii

发明人： Nobuhiro Tsuda ,  Koji Nii

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

公开(公告)号：US06909135B2

公开(公告)日：2005-06-21

申请号：US10096485

申请日：2002-03-13

申请人： Koji Nii ,  Shoji Okuda

发明人： Koji Nii ,  Shoji Okuda

IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/72

CPC分类号： H01L27/1104

摘要： In the semiconductor storage device, a dummy P+ diffusion region which does not contribute to a storage operation is formed in the vicinity of two P+ diffusion regions constituting a storage node. Moreover, a dummy N+ diffusion region which does not contribute to the storage operation is formed in the vicinity of N+ diffusion regions FL210 and FL220 constituting a storage node. Consequently, a part of electrons generated in a P well region PW by irradiation of α rays or neutron rays can be collected into the dummy N+ diffusion region FL250, and a part of holes generated in an N well region NW by the irradiation of the α rays or the neutron rays can be collected into the dummy P+ diffusion region FL150.

摘要翻译： 在半导体存储装置中，在构成存储节点的两个P +扩散区域附近，形成对存储动作无贡献的伪P +扩散区域。 此外，在构成存储节点的N +扩散区域FL 210和FL 220附近形成对存储操作无贡献的虚拟N +扩散区域。 因此，通过α射线或中子射线的照射在P阱区PW中产生的电子的一部分能够被收集到虚拟N +扩散区域FL 250中，并且通过照射 可以将α射线或中子射线收集到虚拟P +扩散区域FL 150中。

公开(公告)号：US06504788B1

公开(公告)日：2003-01-07

申请号：US10141184

申请日：2002-05-09

申请人： Koji Nii ,  Shoji Okuda

发明人： Koji Nii ,  Shoji Okuda

IPC分类号： G11C800

CPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/419

摘要： A semiconductor memory includes a first inverter, a second inverter and a read circuit. The first inverter has its input terminal connected to a first memory node and its output terminal connected to a second memory node. The second inverter is connected in anti-parallel with the first inverter, that is, has its input terminal connected to the second memory node and its output terminal connected to the first memory node. The read circuit includes a first transistor having its gate connected to the first memory node, a second transistor having its gate connected to the second memory node, and a third transistor for connecting the drain of the first transistor and that of the second transistor to a read bit line. The semiconductor memory can improve its soft error resistance without increasing the number of steps of the manufacturing process.

摘要翻译： 半导体存储器包括第一反相器，第二反相器和读取电路。 第一逆变器的输入端连接到第一存储器节点，其输出端连接到第二存储器节点。 第二反相器与第一反相器反并联连接，即其输入端连接到第二存储器节点，其输出端连接到第一存储器节点。 读取电路包括其栅极连接到第一存储器节点的第一晶体管，具有连接到第二存储器节点的栅极的第二晶体管和用于将第一晶体管和第二晶体管的漏极连接到第二晶体管的第三晶体管， 读取位线 半导体存储器可以在不增加制造工艺的步骤的数量的情况下提高其柔软的抗错误性。

公开(公告)号：US08441843B2

公开(公告)日：2013-05-14

申请号：US13317846

申请日：2011-10-31

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US08363456B2

公开(公告)日：2013-01-29

申请号：US12975400

申请日：2010-12-22

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： To improve reliability of a semiconductor device having an SRAM.The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in this order when viewed in a row direction. First and second positive-phase access transistors are disposed in the first p well, first and second driver transistors are disposed in the second p well, and first and second negative-phase access transistors are arranged in the third p well.

摘要翻译： 为了提高具有SRAM的半导体器件的可靠性。 半导体器件具有包括六个n沟道型晶体管和形成在硅衬底上的两个p沟道型晶体管的存储单元。 在硅衬底上，当沿行方向观察时，以该顺序布置第一p阱，第一n阱，第二p阱，第二n阱和第三p阱。 第一和第二正相存取晶体管设置在第一p阱中，第一和第二驱动晶体管设置在第二p阱中，第一和第二负相存取晶体管被布置在第三p阱中。

公开(公告)号：US08310883B2

公开(公告)日：2012-11-13

申请号：US13193258

申请日：2011-07-28

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

摘要翻译： 降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。 驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。 下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路 晶体管。 栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

公开(公告)号：US08072799B2

公开(公告)日：2011-12-06

申请号：US12662029

申请日：2010-03-29

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US07876625B2

公开(公告)日：2011-01-25

申请号：US12555447

申请日：2009-09-08

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

公开(公告)号：US07599214B2

公开(公告)日：2009-10-06

申请号：US12325820

申请日：2008-12-01

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/14 ,  H01L27/11 ,  H01L27/1104

摘要： Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.

摘要翻译： 驱动晶体管的源触点通过使用存储单元内的内部金属线短路。 该金属线与相邻列中的存储单元隔离，并以Z字形形式沿着存储单元列的方向延伸。 可以为每列提供用于传输驱动晶体管的源电压的单独线路，并且也可以以单端口存储器单元的结构中的存储单元列为单位来调节驱动晶体管的源极电压。