公开(公告)号：US07323725B2

公开(公告)日：2008-01-29

申请号：US10962492

申请日：2004-10-13

申请人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

发明人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

IPC分类号： H01L29/739 ,  H01L31/00

CPC分类号： B82Y10/00 ,  H01L29/0817 ,  H01L29/127 ,  H01L29/7371

摘要： The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer disposed between the emitter layer and the base layer; a collector electrode, a base electrode and the emitter layer all connected to an emitter electrode; the quantum dot barrier layer having a plurality of quantum dots being sandwiched between first and second barrier layers from the emitter layer side and the base layer side, respectively and each having a portion that is convex to the base layer; a base layer side interface in the second barrier layer, and collector layer side and emitter layer side interfaces in the base layer having curvatures that are convex to the collector layer corresponding to the convex portions of the quantum dots.

摘要翻译： 本发明涉及一种具有多层结构的半导体器件，该多层结构包括依次由III-V族n型化合物半导体构成的发射极层，基极层和集电极层; 设置在发射极层和基极层之间的量子点势垒层; 集电极，基极和发射极层全部连接到发射极; 所述量子点势垒层分别具有从所述发射极层侧和所述基极侧侧夹在第一和第二阻挡层之间的多个量子点，并且各自具有与所述基极层相对的部分。 第二阻挡层中的基底层侧界面，基底层中的集电极层侧发射极侧接合具有对应于量子点的凸部的集电极层的曲率的曲率。

公开(公告)号：US20050067615A1

公开(公告)日：2005-03-31

申请号：US10962492

申请日：2004-10-13

申请人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

发明人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/737 ,  H01L31/0328

CPC分类号： B82Y10/00 ,  H01L29/0817 ,  H01L29/127 ,  H01L29/7371

摘要： The present invention relates to a semiconductor device comprising a substrate (101); a semiconductor multi-layered structure formed on the substrate (101); the semiconductor multi-layered structure comprising an emitter layer (102), a base layer (105), and a collector layer (107), each composed of a group III-V n-type compound semiconductor and layered in this order; a quantum dot barrier layer (103) disposed between the emitter layer (102) and the base layer (105); a collector electrode (110), a base electrode (111) and an emitter electrode (112) connected to the collector layer (107), the base layer (105) and the emitter layer (102), respectively; the quantum dot barrier layer (103) comprising a plurality of quantum dots (103c); the quantum dots (103) being sandwiched between first and second barrier layers (103a, 103d) from the emitter layer side and the base layer side, respectively; each of the quantum dots (103c) having a convex portion that is convex to the base layer (105); a base layer (105) side interface (d1) in the second barrier layer (103d), and collector layer side and emitter layer side interfaces (d2, d3) in the base layer (105); the interfaces having curvatures (d12, d22, d23) that are convex to the collector layer (107) corresponding to the convex portions of the quantum dots (103c).

摘要翻译： 本发明涉及一种包括衬底（101）的半导体器件; 形成在所述基板（101）上的半导体多层结构; 所述半导体多层结构包括由III-V族N型化合物半导体构成的发射极层（102），基极层（105）和集电极层（107），并且按顺序层叠; 设置在发射极层（102）和基极层（105）之间的量子点势垒层（103）; 分别与集电极层（107）连接的集电极（110），基极（111）和发射极（112），基极层（105）和发射极层（102） 所述量子点势垒层（103）包括多个量子点（103c）; 量子点（103）分别从发射极侧和基极侧夹在第一和第二阻挡层（103a，103d）之间; 每个量子点（103c）具有与基底层（105）凸起的凸部; 第二阻挡层（103d）中的基底层（105）侧界面（d1），以及基底层（105）中的集电极层侧和发射极层侧界面（d2，d3） 具有对应于量子点（103c）的凸部的与集电体层（107）凸起的曲率（d12，d22，d23）的界面。

公开(公告)号：US20060231862A1

公开(公告)日：2006-10-19

申请号：US10542063

申请日：2004-04-14

申请人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

发明人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

IPC分类号： H01L31/00

CPC分类号： H01L29/7371 ,  H01L29/2003 ,  H01L29/7376

摘要： A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

摘要翻译： 本发明的弹道半导体器件包括n型发射极层（102），由n型InGaN制成的基极层（305），n型集电极层（307），发射极阻挡层（103） 在发射极层（102）和基极层（305）之间具有比基底层（305）的带隙大的带隙的集电极阻挡层（306），并且位于基极层（305）和集电极层 （307），并且具有比基底层（305）的带隙大的带隙，并且在10GHz或更高频率下工作。

公开(公告)号：US07414261B2

公开(公告)日：2008-08-19

申请号：US10542063

申请日：2004-04-14

申请人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

发明人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

IPC分类号： H01L29/06

CPC分类号： H01L29/7371 ,  H01L29/2003 ,  H01L29/7376

摘要： A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

摘要翻译： 本发明的弹道半导体器件包括n型发射极层（102），由n型InGaN制成的基极层（305），n型集电极层（307），发射极阻挡层（103） 在发射极层（102）和基极层（305）之间具有比基底层（305）的带隙大的带隙的集电极阻挡层（306），并且位于基极层（305）和集电极层 （307），并且具有比基底层（305）的带隙大的带隙，并且在10GHz或更高频率下工作。

公开(公告)号：US06953954B2

公开(公告)日：2005-10-11

申请号：US10745567

申请日：2003-12-29

申请人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki ,  Toshiya Yokogawa

发明人： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki ,  Toshiya Yokogawa

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/20 ,  H01L29/778 ,  H01L29/80 ,  H01L29/43

CPC分类号： H01L29/1029 ,  H01L29/2003 ,  H01L29/7785

摘要： A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and the channel layer, and these electrodes are formed on the barrier layer through the insulating layer 106.

摘要翻译： 本发明的等离子体振荡切换装置包括半导体基板101， 第一阻挡层103，其由III-V族化合物半导体构成并形成在基板上; 沟道层104，其由III-V族化合物半导体形成并形成在第一阻挡层上; 第二阻挡层105，其由III-V族化合物半导体形成并形成在沟道层上; 源极电极107，栅电极109和漏电极108，其中第一阻挡层包括n型扩散层103a，第二阻挡层包括p型扩散层105a，第二势垒层包括p型扩散层105a， 通道层比第一和第二阻挡层的带隙小，二维电子气体EG在第一阻挡层和沟道层之间的边界处的导带处累积，二维空穴气体HG被积聚 在第二阻挡层和沟道层之间的边界处的价带处，并且这些电极通过绝缘层106形成在阻挡层上。

公开(公告)号：US06861679B2

公开(公告)日：2005-03-01

申请号：US10817035

申请日：2004-04-05

申请人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

发明人： Nobuyuki Otsuka ,  Koichi Mizuno ,  Shigeo Yoshii ,  Asamira Suzuki

IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/338 ,  H01L29/20 ,  H01L29/778 ,  H01L31/0328

CPC分类号： H01L29/7785 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66462 ,  H01L29/7784

摘要： A hetero field effect transistor according to the present invention comprises an InP substrate, a channel layer provided on the InP substrate with a buffer layer disposed between the InP substrate and the channel layer, a spacer layer constituted by a semiconductor having a band gap larger than that of the channel layer formed to hetero-join to the channel layer, and a carrier supply layer formed to be adjacent to the spacer layer, wherein the channel layer comprises a predetermined semiconductor layer constituted by a compound semiconductor represented by a formula GaxIn1−xNyA1−y in which A is As or Sb, composition x satisfies 0≦x≦0.2, and composition y satisfies 0.03≦y≦0.10.

摘要翻译： 根据本发明的异质场效应晶体管包括InP衬底，设置在InP衬底上的沟道层，其中缓冲层设置在InP衬底和沟道层之间，间隔层由具有大于 形成为与沟道层异质连接的沟道层的沟道层和与间隔层相邻形成的载流子供给层，其中沟道层包括由式GaxIn1-xNyA1表示的化合物半导体构成的预定半导体层 -Y，其中A为As或Sb，组成x满足0 <= x <= 0.2，组成y满足0.03 <= Y＆LE; 0.10。

公开(公告)号：US06903383B2

公开(公告)日：2005-06-07

申请号：US10343097

申请日：2001-11-21

申请人： Toshiya Yokogawa ,  Asamira Suzuki ,  Masahiro Deguchi ,  Shigeo Yoshii ,  Hiroyuki Furuya

发明人： Toshiya Yokogawa ,  Asamira Suzuki ,  Masahiro Deguchi ,  Shigeo Yoshii ,  Hiroyuki Furuya

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778 ,  H03F3/60 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/7785 ,  H03F3/601 ,  H03F2200/294

摘要： A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple δ-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple δ-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple δ-doped InAlAs layer (204) as a carrier supplying layer is reduced.

摘要翻译： HEMT具有InAlAs层（202），InGaAs层（203），由交替层叠的n型掺杂层（204a）和未掺杂层（204b）构成的多重δ掺杂InAlAs层（204） InP层（205），肖特基栅电极（210），源极电极（209a）和漏极电极（209b）。 当电流在与InGaAs层（203）和多重δ掺杂的InAlAs层（204）之间的界面相邻的InGaAs层（203）的区域（沟道区）中流动时，可以增加关断状态下的击穿电压 ，同时抵抗通过作为载流子供给层的多个δ-掺杂InAlAs层（204）的载流子的移动。

公开(公告)号：US06437362B1

公开(公告)日：2002-08-20

申请号：US09808651

申请日：2001-03-16

申请人： Asamira Suzuki

发明人： Asamira Suzuki

IPC分类号： H01L310304

摘要： An avalanche photodiode (APD) of the present invention uses a distortion-compensated superlattice multiplication layer (103) for the superlattice multiplication layer. It also uses a multi-layered light-reflecting layer as the light-reflecting layer. This structure of the present invention makes it possible to reduce a layer thickness of the superlattice multiplication layer without decreasing an electron multiplication factor and increasing a dark current. Accordingly, the APD of the present invention shows high response and low operating voltage, while it also maintains low dark current, low noise and broad band at the same time.