摘要:
A tertiary nitrogen atom-containing urethane polymer which comprises units of the following formulas (I) and (II) as the essential components and units of the following formulas (III), (IV) and (V) as the optional components, the content of the unit of the formula (I) being not less than 10 milliequivalents in terms of the tertiary nitrogen atom per kilogram of the urethane polymer, and has a molecular weight of not less than 500: ##STR1## wherein R.sub.1 and R.sub.2 are each a C.sub.1 -C.sub.4 alkyl group and, when taken together with the adjacent nitrogen atom to which they are attached, represent a nitrogen-containing heterocyclic group, R.sub.3 is a C.sub.1 -C.sub.4 alkyl group, R.sub.4 is an optionally branched C.sub.1 -C.sub.8 alkylene group, m is a positive integer and n is zero or a positive integer but m+n is a number which can provide the unit of the formula (I) with a molecular weight of 131 to 6998 and the bondings in the unit of the formula (I) may be in random and/or block, R.sub.5 is a residue of an organic diisocyanate, R.sub.6 is an optionally branched C.sub.1 -C.sub.8 alkylene group, an aromatic group optionally substituted with one or more C.sub.1 -C.sub.4 alkyl groups and/or one or more halogen atoms or a residue of a polyetherdiol thereof, R.sub.7 is a residue of a dicarboxylic acid and R.sub.8 is a residue of a diamine or a residue of a hydrazine, which is effective in improvement of resistance to color change due to gas.
摘要:
A polyurethane composition improved in dyeing property which comprises (A) a polyurethane and (B) a tertiary nitrogen atom-containing polymer incorporated therein in an amount sufficient to stabilize the polyurethane (A), said polymer (B) being the reaction product between (C) a tertiary nitrogen atom-containing diol and an excessive amount of (D) an organic diisocyanate, the terminal isocyanate group in said reaction product being blocked with a monoamine and/or a dialkylhydrazine.
摘要:
Event packets are input to an event handler both in a scheduling phase and in a dispatching phase of an event scheduler. In the scheduling phase, EVCNT of a device of an occurring event is counted up by 1, and in the dispatching phase, EVCNT of a device of a mature event is counted down. In the dispatching phase multiple events are detected based on the EVCNT. If an old status of the top event of the multiple events is equal to a current status of the device, it is decided that event-outstripping has occurred, and events are cancelled. If the old status is not equal to the current status, it is decided that a glitch occurs, and events are modified according to a given mode value. Since the event handler can be implemented by a simple combination logic unit, acceleration performance of a logic simulation accelerator is not adversely affected.
摘要:
A shift register type memory having major and minor loops, wherein the number of bits of the major loop is large enough to permit data of at least two blocks to simultaneously exist in the major loop when one block is constituted of data of bits the number of which is equal to the number of the minor loops, and wherein before a particular block having been transferred out from the minor loops to the major loop is again transferred in to the minor loops after travelling round the major loop, the next block is transferred out from the minor loops to the major loop.
摘要:
A residual magnetic flux estimation device 1 includes a DC power-source control device 11 which controls a DC power source 300 to apply a DC voltage across two terminals of a Δ connection that is a secondary winding or a tertiary winding, a voltage measuring device 12 which measures a terminal voltage at the primary side of a three-phase transformer 200, a computing device 13 that determines a phase having a high voltage between the two phases other than the phase to which the voltage is applied, and a residual magnetic flux measuring device 14 that measures a phase-to-phase residual magnetic flux between the two phases other than the high-voltage phase, and estimates a measured value of the phase-to-phase residual magnetic flux as a maximum residual magnetic flux in the measurement-target three-phase transformer.
摘要:
There is provided a non-volatile semiconductor memory which is capable of establishing a proper reading voltage for an erasure threshold voltage and a proper writing time for the reading voltage by detecting the threshold voltages for writing and erasing in a memory cell array. The present non-volatile semiconductor memory, which is called a flash EEPROM, includes a first memory cell array 1, a second memory cell array 2, a row decoder 3, a line decoder 4, a reading control circuit 5, a writing and erasing control circuit 6, a writing time control circuit 7, a high voltage generating circuit 8, a counter circuit 13, a 1/N circuit 9, and a reading voltage generating circuit 11. The first memory cell array 1 and the second memory cell array 2 are formed on a same memory cell array, and all of the data stored in both memory cell arrays can be erased at once. Thus, all the memory cells in the memory cell array have the same erasure threshold voltage. The first memory cell array 1 is designated to be an area in which data can be freely written, and the second memory cell array 2 is designated as an area for detecting the threshold voltages of the memory cells so that it is not permitted to write in the second memory cell array 2 except when detecting the threshold voltage.
摘要:
As a device used to paint a pattern such as a band, stripe or streak on the surface of an elongate and thin base material continuously supplied, a painting device is composed of at least a painting groove provided across the moving direction of the base material continuously supplied and having an opening formed along its both ends with a width wider than the width of the above-described base material in a manner not to be closed by the base material, a primary pipe communicated with the painted groove and a secondary pipe linked with the primary pipe, so that different kinds of paints are filled into the painting groove through the primary and secondary pipes to paint a pattern such as a band, stripe or streak over the whole surface of the base material in motion. With the opening formed at the both ends of the painting groove in the width direction with a width wider than the latter, it is possible to paint the wole surface of the base material through a single painting process without leaving unpainted areas. This structure prevents any area from being unpainted, eliminates a post-painting processing, and reduces cost and facilities.
摘要:
A laser apparatus includes an electric power supply system and a cooling water supply system. Both the electric terminals of the electric power supply system for connection with an external power cable and ports of the cooling water supply system for communicating with external pipes are placed in the forward part of the laser apparatus for facilitating its maintenance. A storage tank stores cooling water to be supplied to a laser oscillator. Both an ion exchanger and a filter are commonly housed in the tank to downsize the apparatus, to minimize the water leakage and to effectively purify the cooling water. Interchangeable flow control valves are provided for different electric power frequencies. According to the available power frequency an appropriate one of the valves is chosen and connected to internal piping to achieve the desired flow rate of the cooling water supplied to the laser oscillator.
摘要:
The present invention is a simulation apparatus which can shorten the transmission and reception time of events, and unify simulation models to make it possible to use the same language expression as that for an ordinary model to express a real chip. The simulation apparatus comprises a real chip simulation section for carrying out simulation for a portion having an unknown internal logic by using a real chip, a logic simulation hardware section for carrying out simulation for a portion whose internal logic is described, and a high speed dedicated network for transferring event data between the real chip simulation section and the logic simulation hardware section. The simulation apparatus can be applied to hardware accelerators used in logic timing simulation in the field of CAE.
摘要:
A process for purifying crude acetonitrile comprising: (1) a step of contacting crude acetonitrile with nascent oxygen, (2) a step of contacting the acetonitrile from step (1) with a solid base, and (3) a step of removing low-boiling compounds and high-boiling compounds from the acetonitrile from step (2), wherein the step (3) may be effected after the step (1) and before the step (2).