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1.发明授权Laser apparatus and accessible, compact cooling system thereof having interchangeable flow restricting members 失效具有可互换流量限制构件的激光装置和可及的，紧凑的冷却系统
公开(公告)号：US5572538A
公开(公告)日：1996-11-05
申请号：US4581
申请日：1993-01-14
申请人： Minoru Saitoh , Akira Uesugi , Takahiro Uchida
发明人： Minoru Saitoh , Akira Uesugi , Takahiro Uchida
CPC分类号： H01S3/042 , H01S3/0407
摘要： A laser apparatus includes an electric power supply system and a cooling water supply system. Both the electric terminals of the electric power supply system for connection with an external power cable and ports of the cooling water supply system for communicating with external pipes are placed in the forward part of the laser apparatus for facilitating its maintenance. A storage tank stores cooling water to be supplied to a laser oscillator. Both an ion exchanger and a filter are commonly housed in the tank to downsize the apparatus, to minimize the water leakage and to effectively purify the cooling water. Interchangeable flow control valves are provided for different electric power frequencies. According to the available power frequency an appropriate one of the valves is chosen and connected to internal piping to achieve the desired flow rate of the cooling water supplied to the laser oscillator.
摘要翻译： 激光装置包括电力供应系统和冷却水供应系统。 用于与外部电力电缆连接的电力供应系统的电气端子和用于与外部管道连通的冷却水供应系统的端口都放置在激光设备的前部，以便于维护。 储罐储存供应给激光振荡器的冷却水。 离子交换器和过滤器都通常容纳在罐中以减小设备的尺寸，以最小化漏水并且有效地净化冷却水。 为不同的电力频率提供可互换的流量控制阀。 根据可用的功率频率，选择适当的一个阀并将其连接到内部管道，以实现供应给激光振荡器的冷却水的期望流量。
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2.发明授权
公开(公告)号：US5418735A
公开(公告)日：1995-05-23
申请号：US976327
申请日：1992-11-13
申请人： Minoru Saitoh
发明人： Minoru Saitoh
CPC分类号： G06F17/5022
摘要： Event packets are input to an event handler both in a scheduling phase and in a dispatching phase of an event scheduler. In the scheduling phase, EVCNT of a device of an occurring event is counted up by 1, and in the dispatching phase, EVCNT of a device of a mature event is counted down. In the dispatching phase multiple events are detected based on the EVCNT. If an old status of the top event of the multiple events is equal to a current status of the device, it is decided that event-outstripping has occurred, and events are cancelled. If the old status is not equal to the current status, it is decided that a glitch occurs, and events are modified according to a given mode value. Since the event handler can be implemented by a simple combination logic unit, acceleration performance of a logic simulation accelerator is not adversely affected.
摘要翻译： 事件分组在事件调度器的调度阶段和调度阶段都被输入到事件处理程序。 在调度阶段，发生事件的设备的EVCNT向上计数1，在调度阶段，成熟事件的设备的EVCNT被倒计时。 在调度阶段，根据EVCNT检测到多个事件。 如果多个事件的顶级事件的旧状态等于设备的当前状态，则确定事件超出已发生，并且事件被取消。 如果旧状态不等于当前状态，则确定发生毛刺，并根据给定的模式值修改事件。 由于事件处理程序可以通过简单的组合逻辑单元来实现，逻辑模拟加速器的加速性能不会受到不利影响。
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公开(公告)号：US4133043A
公开(公告)日：1979-01-02
申请号：US853276
申请日：1977-11-21
申请人： Minoru Hiroshima , Shigeru Yoshizawa , Nobuo Saito , Atsushi Asano , Hiroshi Suehiro , Minoru Saitoh , Keisuke Mise
发明人： Minoru Hiroshima , Shigeru Yoshizawa , Nobuo Saito , Atsushi Asano , Hiroshi Suehiro , Minoru Saitoh , Keisuke Mise
CPC分类号： G11C19/0875
摘要： A shift register type memory having major and minor loops, wherein the number of bits of the major loop is large enough to permit data of at least two blocks to simultaneously exist in the major loop when one block is constituted of data of bits the number of which is equal to the number of the minor loops, and wherein before a particular block having been transferred out from the minor loops to the major loop is again transferred in to the minor loops after travelling round the major loop, the next block is transferred out from the minor loops to the major loop.
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4.发明授权公开(公告)号：US09291686B2
公开(公告)日：2016-03-22
申请号：US13812255
申请日：2011-07-22
CPC分类号： G01R33/02 , G01R33/0064 , G01R33/12
摘要： A residual magnetic flux estimation device 1 includes a DC power-source control device 11 which controls a DC power source 300 to apply a DC voltage across two terminals of a Δ connection that is a secondary winding or a tertiary winding, a voltage measuring device 12 which measures a terminal voltage at the primary side of a three-phase transformer 200, a computing device 13 that determines a phase having a high voltage between the two phases other than the phase to which the voltage is applied, and a residual magnetic flux measuring device 14 that measures a phase-to-phase residual magnetic flux between the two phases other than the high-voltage phase, and estimates a measured value of the phase-to-phase residual magnetic flux as a maximum residual magnetic flux in the measurement-target three-phase transformer.
摘要翻译： 剩余磁通量估计装置1包括：直流电源控制装置11，其控制直流电源300，跨越Dgr的两个端子施加直流电压; 作为次级绕组或三次绕组的连接，测量三相变压器200的初级侧的端子电压的电压测量装置12，确定在两相之间具有高电压的相位的计算装置13 比施加电压的相位和残留磁通量测量装置14，其测量除了高电压相之外的两相之间的相间残留磁通量，并且估计相位 - 测量目标三相变压器中的相剩余磁通量作为最大剩余磁通量。
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公开(公告)号：US6031762A
公开(公告)日：2000-02-29
申请号：US276507
申请日：1999-03-25
申请人： Minoru Saitoh
发明人： Minoru Saitoh
CPC分类号： G11C16/3495 , G11C16/32 , G11C16/349
摘要： There is provided a non-volatile semiconductor memory which is capable of establishing a proper reading voltage for an erasure threshold voltage and a proper writing time for the reading voltage by detecting the threshold voltages for writing and erasing in a memory cell array. The present non-volatile semiconductor memory, which is called a flash EEPROM, includes a first memory cell array 1, a second memory cell array 2, a row decoder 3, a line decoder 4, a reading control circuit 5, a writing and erasing control circuit 6, a writing time control circuit 7, a high voltage generating circuit 8, a counter circuit 13, a 1/N circuit 9, and a reading voltage generating circuit 11. The first memory cell array 1 and the second memory cell array 2 are formed on a same memory cell array, and all of the data stored in both memory cell arrays can be erased at once. Thus, all the memory cells in the memory cell array have the same erasure threshold voltage. The first memory cell array 1 is designated to be an area in which data can be freely written, and the second memory cell array 2 is designated as an area for detecting the threshold voltages of the memory cells so that it is not permitted to write in the second memory cell array 2 except when detecting the threshold voltage.
摘要翻译： 提供了一种非易失性半导体存储器，其能够通过检测用于存储单元阵列中的写入和擦除的阈值电压，为擦除阈值电压建立适当的读取电压和读取电压的适当写入时间。 被称为闪存EEPROM的本非易失性半导体存储器包括第一存储单元阵列1，第二存储单元阵列2，行解码器3，行解码器4，读取控制电路5，写入和擦除 控制电路6，写入时间控制电路7，高电压产生电路8，计数器电路13，1 / N电路9和读取电压产生电路11.第一存储单元阵列1和第二存储单元阵列 2形成在相同的存储单元阵列上，并且可以一次擦除存储在两个存储单元阵列中的所有数据。 因此，存储单元阵列中的所有存储单元具有相同的擦除阈值电压。 第一存储单元阵列1被指定为可以自由地写入数据的区域，并且第二存储单元阵列2被指定为用于检测存储单元的阈值电压的区域，使得不允许写入 第二存储单元阵列2，除了检测阈值电压之外。
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公开(公告)号：US5620517A
公开(公告)日：1997-04-15
申请号：US470028
申请日：1995-06-06
申请人： Minoru Saitoh
发明人： Minoru Saitoh
CPC分类号： B05D5/061 , B05C5/0266 , B05C9/06 , B44D3/225
摘要： As a device used to paint a pattern such as a band, stripe or streak on the surface of an elongate and thin base material continuously supplied, a painting device is composed of at least a painting groove provided across the moving direction of the base material continuously supplied and having an opening formed along its both ends with a width wider than the width of the above-described base material in a manner not to be closed by the base material, a primary pipe communicated with the painted groove and a secondary pipe linked with the primary pipe, so that different kinds of paints are filled into the painting groove through the primary and secondary pipes to paint a pattern such as a band, stripe or streak over the whole surface of the base material in motion. With the opening formed at the both ends of the painting groove in the width direction with a width wider than the latter, it is possible to paint the wole surface of the base material through a single painting process without leaving unpainted areas. This structure prevents any area from being unpainted, eliminates a post-painting processing, and reduces cost and facilities.
摘要翻译： 作为在连续供给的细长薄基材的表面上形成带状，条状或条纹等图案的装置，由至少连续地设置在基材的移动方向上的涂装槽构成涂装装置 并且具有沿着其两端形成的开口，其宽度大于上述基材的宽度，不会被基材封闭，与涂漆槽连通的主管和与该凹槽连通的次级管 主管，使得通过主管和辅管将不同种类的油漆填充到油漆槽中，以在基材的整个表面上运动地涂覆诸如带，条纹或条纹的图案。 由于在宽度方向的宽度方向的两端形成有开口宽度大于后者的开口，因此可以通过单一的涂布工序对基材的表面进行涂漆，而不会留下未上漆的区域。 这种结构可防止任何区域不上漆，消除后期加工，并降低成本和设施。
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公开(公告)号：US5838593A
公开(公告)日：1998-11-17
申请号：US539775
申请日：1995-10-05
CPC分类号： G06F11/261 , G06F17/5022
摘要： The present invention is a simulation apparatus which can shorten the transmission and reception time of events, and unify simulation models to make it possible to use the same language expression as that for an ordinary model to express a real chip. The simulation apparatus comprises a real chip simulation section for carrying out simulation for a portion having an unknown internal logic by using a real chip, a logic simulation hardware section for carrying out simulation for a portion whose internal logic is described, and a high speed dedicated network for transferring event data between the real chip simulation section and the logic simulation hardware section. The simulation apparatus can be applied to hardware accelerators used in logic timing simulation in the field of CAE.
摘要翻译： 本发明是能够缩短事件发送和接收时间的模拟装置，并且使仿真模型统一起来，使得能够使用与普通模型相同的语言表达来表达实际的芯片。 仿真装置包括一个实际芯片仿真部分，用于通过使用真实芯片对具有未知内部逻辑的部分进行仿真，用于对其内部逻辑被描述的部分进行仿真的逻辑模拟硬件部分和高速专用 用于在实际芯片仿真部分和逻辑仿真硬件部分之间传送事件数据的网络。 仿真设备可以应用于CAE领域逻辑定时仿真中使用的硬件加速器。
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公开(公告)号：US5629443A
公开(公告)日：1997-05-13
申请号：US371180
申请日：1995-01-11
IPC分类号： C07C253/34
CPC分类号： C07C253/34
摘要： A process for purifying crude acetonitrile comprising: (1) a step of contacting crude acetonitrile with nascent oxygen, (2) a step of contacting the acetonitrile from step (1) with a solid base, and (3) a step of removing low-boiling compounds and high-boiling compounds from the acetonitrile from step (2), wherein the step (3) may be effected after the step (1) and before the step (2).
摘要翻译： 一种净化粗乙腈的方法，包括：（1）使粗乙腈与新生氧接触的步骤，（2）使步骤（1）的乙腈与固体碱接触的步骤，和（3） 沸腾化合物和来自步骤（2）的乙腈的高沸点化合物，其中步骤（3）可以在步骤（1）之后和步骤（2）之前进行。
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9.发明授权
公开(公告)号：US5561535A
公开(公告)日：1996-10-01
申请号：US297050
申请日：1994-08-26
IPC分类号： B41J29/40 , B41J29/42 , G03G15/36 , G03G21/00 , H04N1/00 , H04N1/32 , H04N1/387 , H04N1/40 , G03G15/04
CPC分类号： H04N1/32133 , G03G15/36 , G03G15/502 , H04N1/00352 , H04N1/00384 , H04N1/00397 , H04N1/00411 , H04N1/00498 , H04N2201/3214 , H04N2201/3271
摘要： An image forming apparatus into which additional information and the write area are inputted when reading a document image and which synthesizes the additional information as well as the document image read and prints the data on write area inputted, and especially that which prints the additional information in an area between punch holes for filing.
摘要翻译： 一种图像形成装置，当读取文档图像并且合成附加信息以及文档图像读取并在输入的写入区域上打印数据时，附加信息和写入区域被输入到其中，并且特别是将附加信息打印到 打孔孔之间的区域。
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10.发明授权Method and apparatus for logic simulation of logic system including multi-port memory 失效包括多端口存储器的逻辑系统的逻辑仿真方法和装置
公开(公告)号：US5511011A
公开(公告)日：1996-04-23
申请号：US054258
申请日：1993-04-30
申请人： Minoru Saitoh
发明人： Minoru Saitoh
CPC分类号： G06F17/5022
摘要： A simulation apparatus and method for a logic circuit including a multi-port RAM effects simulation by provisionally representing input and output ports by use of a plurality of memory primitives and effecting the operation equivalent to the operation of the multi-port RAM. The address, data input and write enable terminals of input side memory primitives are supplied with write addresses, data inputs and write enable signals, respectively, and the chip select terminals thereof are supplied with "0" from a logic primitive. The write enable signals are also supplied to an AND logic primitive. The address terminals of output side memory primitives are supplied with respective read addresses, the data input terminals thereof are supplied with an output of the AND logic primitive, the chip select terminals thereof are supplied with "0" from a logic primitive, and the write enable terminals thereof are supplied with "1" from a logic primitive. Data outputs are derived from the respective output side memory primitives.
摘要翻译： 一种包括多端口RAM的逻辑电路的模拟装置和方法，其通过使用多个存储器原语临时表示输入和输出端口并实现与多端口RAM的操作相当的操作来影响模拟。 输入侧存储器基元的地址，数据输入和写使能端分别被提供写入地址，数据输入和写使能信号，并且其逻辑基元被提供“0”。 写使能信号也被提供给AND逻辑基元。 输出侧存储器原语的地址端子被提供有相应的读地址，其数据输入端被提供有AND逻辑基元的输出，其选择选择端从逻辑基元提供“0” 使能端子从逻辑基元提供“1”。 数据输出从相应的输出侧存储器基元导出。
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