公开(公告)号：US20080001554A1

公开(公告)日：2008-01-03

申请号：US11646720

申请日：2006-12-27

申请人： Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

发明人： Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

IPC分类号： H05B41/36

CPC分类号： H05B41/2858 ,  Y02B20/186

摘要： Disclosed is a technique suitable for performing a stable protection function while satisfying a standard specification in the implementation of an LCC of a digital inverter for an LCD backlight. The LCC of a digital inverter for an LCD backlight comprises: a transformer which raises a AC power supplied from the inverter to an AC voltage of a high voltage for lighting a lamp; a voltage/current detection unit for detecting at least one of the current and voltage supplied to the lamp; an A/D converter for converting the detected voltage/current value of analog to a digital value; and an MCU which induces an LCC check point after the start of a striking process, compares at least one of the output current value and voltage value from the transformer with a preset reference value on the basis of an output signal of the A/D converter and then shuts down the inverter when the output current value or voltage value is determined to be abnormal.

摘要翻译： 公开了一种适用于执行稳定保护功能的技术，同时满足用于LCD背光的数字逆变器的LCC的实施中的标准规格。 用于LCD背光的数字逆变器的LCC包括：变换器，其将从逆变器提供的AC电力提升到用于点亮灯的高电压的AC电压; 电压/电流检测单元，用于检测提供给灯的电流和电压中的至少一个; 用于将检测到的模拟电压/电流值转换为数字值的A / D转换器; 以及在开始触发处理之后引起LCC检查点的MCU，根据A / D转换器的输出信号，将来自变压器的输出电流值和电压值中的至少一个与预设的参考值进行比较 然后当输出电流值或电压值被确定为异常时，关闭逆变器。

公开(公告)号：US07911147B2

公开(公告)日：2011-03-22

申请号：US11646720

申请日：2006-12-27

申请人： Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

发明人： Oh-Sang Kwon ,  Chang-Ho Lee ,  Yong-Kon Lee

IPC分类号： H05B37/00

CPC分类号： H05B41/2858 ,  Y02B20/186

摘要： A limited current circuit of this invention comprising: a transformer that raises an alternating current (AC) power supplied from the digital inverter to an AC voltage of a high voltage to light a lamp; a voltage/current detection unit that detects at least one of the current and voltage supplied to the lamp; an A/D converter that converts the detected voltage/current value of analog to a digital value; and a microcontroller unit (MCU) that induces an LCC check point after the start of a striking process, compares at least one of the output current value and voltage value from the transformer with a preset reference value on the basis of an output signal of the A/D converter and then shuts down the inverter when the output current value or voltage value is determined to be abnormal, wherein the reference value comprises at least one of the current value and voltage value measured at the LCC check point when an object having noninductive resistance is not contacted to the inverter.

摘要翻译： 本发明的有限电流电路包括：变压器，其将从数字逆变器提供的交流电（AC）电力提高到高电压的AC电压以点亮灯; 电压/电流检测单元，其检测提供给所述灯的电流和电压中的至少一个; A / D转换器，其将检测到的模拟电压/电流值转换为数字值; 以及在触发过程开始之后引起LCC检查点的微控制器单元（MCU），将来自变压器的输出电流值和电压值中的至少一个与预设的参考值进行比较，基于输出信号 A / D转换器，然后当输出电流值或电压值被确定为异常时，关闭逆变器，其中参考值包括当具有非导体的物体时在LCC检查点测量的电流值和电压值中的至少一个 电阻不接触逆变器。

公开(公告)号：US5598116A

公开(公告)日：1997-01-28

申请号：US550332

申请日：1995-10-30

申请人： Oh-Sang Kwon

发明人： Oh-Sang Kwon

IPC分类号： G04F10/04 ,  G01R23/10 ,  G01R31/3193 ,  G04F10/00 ,  H03K9/08

CPC分类号： G01R29/0273 ,  G01R23/10 ,  G01R31/31937 ,  G04F10/00

摘要： A pulse duration measuring apparatus generates a clock signal in the form of a clock pulse train having a period(T) and delays the clock signal and provides N-1 number of delayed clock signals, each of the delayed clock signals delayed by a delay time((T/N)*i), N being a positive integer and i being 1 to N-1 and counts the number of the clock pulses contained in the clock signal and each of the delayed clock signals, respectively, during the duration(Y) of the input pulse signal(I) and providing the count values. A pulse duration measuring apparatus detects a maximum counted value(n) among the counted values provided from the counting means and calculates the duration(Y) of the input pulse signal(I) based on the maximum count value(n).

摘要翻译： 脉冲宽度测量装置产生具有周期（T）的时钟脉冲串形式的时钟信号，并延迟时钟信号并提供N-1个延迟的时钟信号，每个延迟的时钟信号延迟延迟时间 （（T / N）* i），N是正整数，i是1到N-1，并且在持续时间（分钟）期间分别对包括在时钟信号和每个延迟的时钟信号中的时钟脉冲的数目进行计数 Y）并提供计数值。 脉冲宽度测量装置检测从计数装置提供的计数值中的最大计数值（n），并基于最大计数值（n）计算输入脉冲信号（I）的持续时间（Y）。

公开(公告)号：US5373323A

公开(公告)日：1994-12-13

申请号：US145500

申请日：1993-11-01

申请人： Oh-Sang Kwon

发明人： Oh-Sang Kwon

IPC分类号： H04N1/17 ,  G09G5/00 ,  H04N7/01

CPC分类号： H04N7/012 ,  G09G5/00 ,  G09G2310/0229

摘要： A data converter for converting interlaced image data into a non-interlaced format is disclosed. The converter comprises a buffer memory capable of storing upto N such scan lines of the interlaced image data for performing, per input pixel clock pulse, a read and then a write operation, wherein the N represents the number of scan lines per field; a horizontal address generator for, upon receiving each of input pixel clock pulses, generating a horizontal address by sequentially counting the number of pixel clock pulses received after each of input H/SYNC pulses received; and a vertical address generator for generating, upon receiving each of the input H/SYNC pulses, generating one of a series of vertical addresses for outputting the interlaced image data in the non-interlaced format.

摘要翻译： 公开了一种用于将隔行图像数据转换为非隔行扫描格式的数据转换器。 该转换器包括缓冲存储器，其能够存储多达N个这样的隔行图像数据的扫描线，用于每个输入像素时钟脉冲执行读取和写入操作，其中N表示每个场的扫描线数; 水平地址发生器，用于在接收到每个输入像素时钟脉冲之后，通过对接收到的每个输入H / SYNC脉冲之后接收到的像素时钟脉冲的数量进行顺序计数来产生水平地址; 以及垂直地址发生器，用于在接收到每个输入H / SYNC脉冲时产生一系列垂直地址中的一个，用于以非隔行格式输出隔行图像数据。

公开(公告)号：US5497239A

公开(公告)日：1996-03-05

申请号：US253479

申请日：1994-06-03

申请人： Oh-Sang Kwon

发明人： Oh-Sang Kwon

IPC分类号： G11B20/10 ,  H04N5/92 ,  H04N5/926 ,  H04N7/26 ,  H04N9/79 ,  H04N5/76

CPC分类号： H04N5/9264 ,  H04N19/40 ,  H04N9/7921

摘要： An apparatus having a recording and reproducing unit for recording and reproducing an encoded video signal received from a transmitter comprises a first, a second and a third recording paths through which the encoded video signal is processed in a first recording mode, a second recording mode and a third recording mode in order to selectively record the processed video signal; and a fourth, a fifth and a sixth reproduction paths through which the video signal recorded in the first, the second or the third recording mode is retrieved by the recording and reproducing unit and processed for the displaying thereof.

摘要翻译： 具有用于记录和再现从发射机接收的编码视频信号的记录和再现单元的装置包括第一，第二和第三记录路径，编码视频信号通过该第一记录路径以第一记录模式被处理，第二记录模式和 第三记录模式，以选择性地记录经处理的视频信号; 以及第四，第五和第六再现路径，通过记录和再现单元检索以第一，第二或第三记录模式记录的视频信号并进行处理以进行显示。

公开(公告)号：US5457481A

公开(公告)日：1995-10-10

申请号：US133622

申请日：1993-10-07

申请人： Chang Sohn ,  Oh-Sang Kwon

发明人： Chang Sohn ,  Oh-Sang Kwon

IPC分类号： H04N19/50 ,  G06T7/20 ,  G11C8/00 ,  G11C8/04 ,  H04N19/42 ,  H04N19/423 ,  H04N19/426 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/70 ,  G09G1/02

CPC分类号： G06T7/2013 ,  G11C8/00 ,  G11C8/04 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61 ,  G06T2207/10016 ,  G06T2207/20052

摘要： A memory apparatus for use in a receiver for decoding video signals comprises a first memory for storing an image frame; a second memory for storing current pixel data temporally and providing the same to said first memory; an address generator for generating address signals for sequentially addressing two-dimensional pixels in the blocks; a delay unit for delaying said address signals by a predetermined delay time in generating write address signals for said first memory; an offset unit for comparing the said address signals with an offset address so as to prohibit the provision of write address signals to said first memory until one of said address signals reaches to said offset address; and a control circuit for selectively providing the read address signals and the write address signals to said first memory.

摘要翻译： 一种用于解码视频信号的接收机中的存储装置包括用于存储图像帧的第一存储器; 用于暂时存储当前像素数据并将其提供给所述第一存储器的第二存储器; 地址发生器，用于产生用于顺序寻址块中的二维像素的地址信号; 延迟单元，用于在产生用于所述第一存储器的写入地址信号时，将所述地址信号延迟预定的延迟时间; 偏移单元，用于将所述地址信号与偏移地址进行比较，以便禁止向所述第一存储器提供写入地址信号，直到所述地址信号之一到达所述偏移地址; 以及用于选择性地将所述读取地址信号和所述写入地址信号提供给所述第一存储器的控制电路。

公开(公告)号：US5442402A

公开(公告)日：1995-08-15

申请号：US127256

申请日：1993-09-23

申请人： Chang Sohn ,  Oh-Sang Kwon

发明人： Chang Sohn ,  Oh-Sang Kwon

IPC分类号： H04N5/907 ,  H04N5/92 ,  H04N7/24 ,  H04N19/423 ,  H04N19/436 ,  H04N19/46 ,  H04N19/50 ,  H04N19/503 ,  H04N19/70 ,  H04N7/32

CPC分类号： H04N19/423 ,  H04N19/61

摘要： A high speed modular memory adapted for use in a decoding system of motion compensated prediction coded image data, comprises: 2.sup.N memory modules each comprising a two dimensional memory array with an address register for storing different pixels of a frame of the image data, wherein said N is a positive integer; a read/write signal generator for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a horizontal and a vertical addresses for each of the 2.sup.N memory modules in response to a motion vector separated into a horizontal motion vector and a vertical motion vector and the read/write control signal; a data bus for communicating the image data with the 2.sup.N memory modules; and an order changer which changes within the data bus positions of the data simultaneously read from the 2.sup.N memory modules within the data bus in response to the horizontal motion vector.

摘要翻译： 适用于运动补偿预测编码图像数据的解码系统的高速模块化存储器包括：2N个存储器模块，每个存储器模块包括具有用于存储图像数据的帧的不同像素的地址寄存器的二维存储器阵列，其中所述 N是正整数; 读/写信号发生器，用于响应于来自图像数据的帧同步信号产生读/写信号; 地址发生器，用于响应于分离成水平运动矢量的运动矢量和垂直运动矢量以及读/写控制信号，同时为每个2N个存储器模块生成水平和垂直地址; 用于将图像数据与2N个存储器模块通信的数据总线; 以及顺序改变器，其响应于水平运动矢量，在数据总线内从2N个存储器模块同时读取的数据的数据总线位置内改变。

公开(公告)号：US5532747A

公开(公告)日：1996-07-02

申请号：US308237

申请日：1994-09-19

申请人： Sang-Ho Yoon ,  Oh-Sang Kwon

发明人： Sang-Ho Yoon ,  Oh-Sang Kwon

IPC分类号： H04N19/50 ,  G06T9/00 ,  H04N19/423 ,  H04N19/44 ,  H04N19/46 ,  H04N19/503 ,  H04N19/51 ,  H04N19/523 ,  H04N19/59 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/91 ,  H04N7/50

CPC分类号： H04N19/523

摘要： A method for decoding an encoded image signal supplied in the form of a series of encoded image frames, each of the encoded image frames being divided into a multiplicity of macroblocks of pixels, each of the macroblocks having an associated half-pixel resolution motion vector which represents a translatory motion of the macroblock between a present and its preceding frames of the encoded image signal to a half-pixel accuracy, comprises: providing differential pixels of a differential macroblock in a first predetermined scanning order by performing entropy decoding, inverse quantization and inverse transformation on the pixels in each macroblock of the present frame; scanning the differential pixels so as to provide scan converted differential pixels of a scan converted differential macroblock in a second predetermined scanning order; providing half-pixel resolution pixels of a half-pixel resolution macroblock in the second predetermined scanning order by accessing, under a control of the half-pixel resolution motion vector, the pixels in the previous frame in an order corresponding to the second predetermined scanning order and, depending on the half-pixel resolution motion vector, performing a spatial interpolation on the pixels in the previous frame; and adding, on a pixel-by-pixel basis, the scan converted differential macroblock to the half-pixel resolution macroblock, to thereby form a reconstructed macroblock of the present frame.

摘要翻译： 一种用于解码以一系列编码图像帧的形式提供的编码图像信号的方法，每个编码图像帧被分成多个像素宏块，每个宏块具有相关联的半像素分辨率运动矢量，其中， 表示在编码图像信号的当前帧和其前一帧之间的宏块的平移运动为半像素精度，包括：通过执行熵解码，逆量化和反演来提供第一预定扫描顺序的差分宏块的差分像素 对当前帧的每个宏块中的像素进行变换; 扫描差分像素，以便以第二预定扫描顺序提供扫描转换的差分宏块的扫描转换的差分像素; 通过在半像素分辨率运动矢量的控制下，以与第二预定扫描顺序对应的顺序访问前一帧中的像素，提供第二预定扫描顺序的半像素分辨率宏块的半像素分辨率像素 并且根据半像素分辨率运动矢量，对前一帧中的像素执行空间插值; 并且在逐像素的基础上将扫描转换的差分宏块添加到半像素分辨率宏块，从而形成本帧的重建宏块。

公开(公告)号：US5418658A

公开(公告)日：1995-05-23

申请号：US231931

申请日：1994-04-25

申请人： Oh-Sang Kwon

发明人： Oh-Sang Kwon

IPC分类号： G11B20/10 ,  G06T9/00 ,  H04N5/92 ,  H04N5/926 ,  H04N9/79 ,  H04N19/00 ,  H04N19/126 ,  H04N19/152 ,  H04N19/423 ,  H04N19/593 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91 ,  G11B5/09 ,  G11B15/12 ,  H04N5/76 ,  H04N5/78

CPC分类号： H04N5/9264 ,  H04N19/152 ,  H04N19/40 ,  H04N19/50 ,  H04N9/7921

摘要： An apparatus for recording and reproducing an encoded video signal from a source encoder comprises a decoder for performing a decoding process for the encoded video signal to produce a decoded video signal, an encoder block for compressing the decoded video signal using a spatial correlation to produce an intra mode compression signal, a buffer memory for storing the intra mode compression signal, a mode controller for generating a clock pulse used to read out data in the buffer memory in accordance with a longer playing time recording and a normal playing time recording and a recording and reproducing unit for recording and reproducing the intra mode compression signal read from the buffer memory.

摘要翻译： 一种用于从源编码器记录和再现编码视频信号的装置包括：解码器，用于对编码视频信号执行解码处理以产生解码视频信号;编码器块，用于使用空间相关压缩解码的视频信号， 帧内模式压缩信号，用于存储帧内模式压缩信号的缓冲存储器，用于根据较长的播放时间记录和正常播放时间记录和记录产生用于读出缓冲存储器中的数据的时钟脉冲的模式控制器 以及用于记录和再现从缓冲存储器读取的帧内模式压缩信号的再现单元。

公开(公告)号：US5408251A

公开(公告)日：1995-04-18

申请号：US146425

申请日：1993-10-29

申请人： Oh-Sang Kwon

发明人： Oh-Sang Kwon

IPC分类号： G06F12/02 ,  G06T1/60 ,  G09G5/39 ,  H04N5/907 ,  G09G1/02

CPC分类号： G09G5/39 ,  G06F12/0207 ,  G09G2360/12

摘要： Disclosed herein is a memory system for storing a two dimensional digitized image signal consisting of a plurality of pixels arranged in (2.sup.M +X) columns and (2.sup.N +Y) rows, wherein X and Y do not exceed 2.sup.M-2 and 2.sup.N-1 respectively, and M and N are integers, comprising: a virtual address generator for generating (M+N+2) bits of a virtual address having (M+1) bits of a horizontal address component representing said (2.sup.M +X) columns and (N+1) bits of a vertical address component representing said (2.sup.N +Y) rows; a memory, having storage locations of 2.sup.M+N+1, for storing the two dimensional digitized image signal, each of the storage locations capable of storing one pixel data therein and addressable by (M+N+1 bits) of a physical address; and address mapping circuitry for changing the virtual address to the physical address.

摘要翻译： 这里公开了一种用于存储由（2M + X）列和（2N + Y）行排列的多个像素组成的二维数字化图像信号的存储系统，其中X和Y不超过2M-2和2N-1 并且M和N是整数，包括：虚拟地址发生器，用于产生具有表示所述（2M + X）列的水平地址分量的（M + 1）位的虚拟地址（M + N + 2）位，以及 （2N + Y）行的垂直地址分量的（N + 1）位; 存储器，具有2M + N + 1的存储位置，用于存储二维数字化图像信号，每个存储位置能够存储一个像素数据，并且可通过物理地址的（M + N + 1位）寻址; 以及用于将虚拟地址改变为物理地址的地址映射电路。