公开(公告)号：US09812448B2

公开(公告)日：2017-11-07

申请号：US14963271

申请日：2015-12-09

申请人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

发明人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L27/02 ,  H01L27/11 ,  H01L29/51 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/28088 ,  H01L21/82345 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

摘要： Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.

公开(公告)号：US20160181412A1

公开(公告)日：2016-06-23

申请号：US14963271

申请日：2015-12-09

申请人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

发明人： Oh-Seong Kwon ,  Jin-Kyu Jang ,  Wan-Don Kim ,  Hoon-Joo Na ,  Sang-Jin Hyun

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L27/088 ,  H01L21/28088 ,  H01L21/82345 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

摘要： Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.

摘要翻译： 提供了一种半导体器件，其被配置为通过在阻挡层之间形成氧化物层来阻挡物理扩散路径，以防止杂质通过阻挡层之间的物理扩散路径扩散，以及制造半导体器件的方法。 半导体器件包括：形成在基板上的栅极绝缘层，形成在栅极绝缘层上的第一势垒层，形成在第一势垒层上的氧化物层，氧化物层包括通过氧化包含在第一势垒中的材料形成的氧化物 形成在氧化物层上的第二阻挡层，形成在第二阻挡层上的栅电极和设置在基板中的栅电极的相对侧的源极/漏极。

公开(公告)号：US09780183B2

公开(公告)日：2017-10-03

申请号：US14989154

申请日：2016-01-06

申请人： Wan-Don Kim ,  Oh-Seong Kwon ,  Hoon-Joo Na ,  Hyeok-Jun Son ,  Jae-Yeol Song ,  Sung-Kee Han ,  Sang-Jin Hyun

发明人： Wan-Don Kim ,  Oh-Seong Kwon ,  Hoon-Joo Na ,  Hyeok-Jun Son ,  Jae-Yeol Song ,  Sung-Kee Han ,  Sang-Jin Hyun

IPC分类号： H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L29/4966 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/4238

摘要： A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

公开(公告)号：US20110180879A1

公开(公告)日：2011-07-28

申请号：US12972961

申请日：2010-12-20

申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L23/522 ,  H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

摘要翻译： 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US09287199B2

公开(公告)日：2016-03-15

申请号：US12972961

申请日：2010-12-20

申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L23/522 ,  H01L23/485 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L29/94

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

摘要翻译： 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US08748251B2

公开(公告)日：2014-06-10

申请号：US13528068

申请日：2012-06-20

申请人： Hoon-Joo Na ,  Hyung-Seok Hong ,  Sang-Bom Kang ,  Hyeok-Jun Son ,  June-Hee Lee ,  Jeong-Hee Han ,  Sang-Jin Hyun

发明人： Hoon-Joo Na ,  Hyung-Seok Hong ,  Sang-Bom Kang ,  Hyeok-Jun Son ,  June-Hee Lee ,  Jeong-Hee Han ,  Sang-Jin Hyun

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/4958 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

摘要翻译： 制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层 层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。 可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层 塞子。

公开(公告)号：US08580629B2

公开(公告)日：2013-11-12

申请号：US13241871

申请日：2011-09-23

申请人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

发明人： Hong-Bae Park ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

摘要翻译： 制造半导体器件的方法可以包括：制备其中限定了第一和第二区域的衬底; 在衬底上形成包括第一和第二沟槽的层间绝缘膜; 沿着层间绝缘膜的上表面，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面形成包含Al和N的功函数控制膜; 在形成在第二区域中的功函数控制膜上形成掩模图案; 将工作功能控制材料注入到形成在第一区域中的功函数控制膜中，以控制形成在第一区域中的功函数控制膜的功函数; 去除掩模图案; 以及形成第一金属栅电极以填充所述第一沟槽并形成第二金属栅电极以填充所述第二沟槽。

公开(公告)号：US20160204108A1

公开(公告)日：2016-07-14

申请号：US15054571

申请日：2016-02-26

申请人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

摘要翻译： 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：US08557651B2

公开(公告)日：2013-10-15

申请号：US13040472

申请日：2011-03-04

申请人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Hag-Ju Cho ,  Sang-Jin Hyun ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Hag-Ju Cho ,  Sang-Jin Hyun ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/28

摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.

摘要翻译： 在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。 蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。 因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

公开(公告)号：US20120122309A1

公开(公告)日：2012-05-17

申请号：US13241871

申请日：2011-09-23

申请人： Hong-Bae PARK ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

发明人： Hong-Bae PARK ,  Sang-Jin Hyun ,  Hu-Yong Lee ,  Hoon-Joo Na ,  Jeong-Hee Han ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.

摘要翻译： 制造半导体器件的方法可以包括：制备其中限定了第一和第二区域的衬底; 在衬底上形成包括第一和第二沟槽的层间绝缘膜; 沿着层间绝缘膜的上表面，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面形成包含Al和N的功函数控制膜; 在形成在第二区域中的功函数控制膜上形成掩模图案; 将工作功能控制材料注入到形成在第一区域中的功函数控制膜中，以控制形成在第一区域中的功函数控制膜的功函数; 去除掩模图案; 以及形成第一金属栅电极以填充所述第一沟槽并形成第二金属栅电极以填充所述第二沟槽。