利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

116 条记录 (耗时 0.047 秒)

    Controlling current transients in a processor
    3.
    发明授权
    Controlling current transients in a processor 有权
    控制处理器中的电流瞬变

    公开(公告)号：US09092210B2

    公开(公告)日：2015-07-28

    申请号：US13307529

    申请日：2011-11-30

    申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    IPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/32

    CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

    摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

    Controlling Current Transients In A Processor
    4.
    发明申请
    Controlling Current Transients In A Processor 有权
    控制处理器中的电流瞬变

    公开(公告)号：US20120166854A1

    公开(公告)日：2012-06-28

    申请号：US13307529

    申请日：2011-11-30

    申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    IPC分类号： G06F1/26

    CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

    摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

    Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
    6.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates 有权
    能量效率和节能的方法，装置和系统，包括在变化的唤醒速率下优化C状态选择

    公开(公告)号：US08799687B2

    公开(公告)日：2014-08-05

    申请号：US13339284

    申请日：2011-12-28

    申请人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    发明人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F13/24 ,  G06F15/00

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

    摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

    摘要翻译： 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES
    7.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES 有权
    能源效率和能源保护的方法，装置和系统，包括在可变的唤醒速率下优化C状态选择

    公开(公告)号：US20130097437A9

    公开(公告)日：2013-04-18

    申请号：US13339284

    申请日：2011-12-28

    申请人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    发明人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

    摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

    摘要翻译： 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

    Package level power state optimization
    8.
    发明授权
    Package level power state optimization 有权
    封装级电源状态优化

    公开(公告)号：US09026829B2

    公开(公告)日：2015-05-05

    申请号：US12890652

    申请日：2010-09-25

    申请人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

    发明人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F12/08

    CPC分类号： G06F1/3203 ,  G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

    摘要： Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

    摘要翻译： 描述了优化封装级功率状态使用的方法和设备。 在一个实施例中，处理器控制逻辑接收到进入较低功耗状态（诸如封装级更深的睡眠状态）的请求。 控制逻辑确定进入较低功耗状态的最后一个入口与当前时间之间的时差或增量。 然后，控制逻辑基于时间差与对应于较低功耗状态的阈值的比较，引起最后一级高速缓冲存储器的刷新。 还要求和公开其它实施例。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES
    9.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES 审中-公开
    能源效率和能源保护的方法，装置和系统，包括在可变的唤醒速率下优化C状态选择

    公开(公告)号：US20140317430A1

    公开(公告)日：2014-10-23

    申请号：US14317239

    申请日：2014-06-27

    申请人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    发明人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

    摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

    摘要翻译： 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES
    10.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING OPTIMIZING C-STATE SELECTION UNDER VARIABLE WAKEUP RATES 有权
    能源效率和能源保护的方法，装置和系统，包括在可变的唤醒速率下优化C状态选择

    公开(公告)号：US20120191995A1

    公开(公告)日：2012-07-26

    申请号：US13339284

    申请日：2011-12-28

    申请人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    发明人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

    摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

    摘要翻译： 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。