公开(公告)号：US08570067B2

公开(公告)日：2013-10-29

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US20080157817A1

公开(公告)日：2008-07-03

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US20060038620A1

公开(公告)日：2006-02-23

申请号：US10924145

申请日：2004-08-23

申请人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

发明人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/18

摘要： A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

摘要翻译： 电路包括锁相环电路和连续锁相环校准电路。 连续锁相环校准电路可操作地耦合到PLL电路，并且基于来自参考电压电路的参考电压产生连续校准信号，以连续地校准PLL电路。

公开(公告)号：US06268744B1

公开(公告)日：2001-07-31

申请号：US09609022

申请日：2000-06-30

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K190185

CPC分类号： H03K19/00315 ,  H03K19/018585

摘要： A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

摘要翻译： 缓冲电路在例如I / O焊盘的输出缓冲器上使用单栅极氧化物预缓冲器电压电平移位电路，以适应不同的I / O焊盘电源电压，同时保持跨越边界的正常工作电压（劣化电平） 的形成缓冲器的单栅极氧化物器件。 单栅极氧化物输出缓冲器可以在几种不同的电源电压下工作。 预缓冲器电压电平移位电路包括多电源电压移位电路，其具有被耦合以产生到缓冲器输出缓冲器的预缓冲器输出信号的信号栅极氧化器件。 单栅极氧化物交叉耦合有源负载耦合到多电源电压电平移位电路，并向级联缓冲晶体管中的至少一个提供合适的驱动电压。

公开(公告)号：US6160430A

公开(公告)日：2000-12-12

申请号：US274456

申请日：1999-03-22

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K19/003 ,  H03L7/00

CPC分类号： H03K19/00315

摘要： A powerup sequencing circuit and method generates an artificial supply voltage until the actual supply voltage is at a suitable level. An artificial supply source, such as a pull up circuit, is coupled to a node that receives a first supply voltage, such as an I/O buffer voltage. The pull up circuit is also coupled to an isolatable source voltage node. The isolatable source voltage node is the node that causes the actual second supply voltage. A temporary isolation circuit is operatively coupled to the pull up circuit and is operatively interposed between the node that receives the first supply voltage and the isolatable source voltage node. The pull up circuit provides a temporary or artificial second supply voltage level to an on chip circuit, such as an I/O buffer circuit or other suitable circuit that may, for example, be multi-voltage supply dependent. The temporary supply voltage is provided to the on chip circuit during powerup and the temporary isolation circuit operatively isolates the isolatable source voltage node until the second supply voltage reaches a suitable level and turns off the temporary isolation circuit.

摘要翻译： 上电顺序电路和方法产生人造电源电压，直到实际电源电压处于适当的电平。 诸如上拉电路的人造供电源耦合到接收诸如I / O缓冲器电压的第一电源电压的节点。 上拉电路还耦合到可隔离的源极电压节点。 可分离源电压节点是导致实际第二电源电压的节点。 临时隔离电路可操作地耦合到上拉电路，并且可操作地插入在接收第一电源电压的节点和可隔离源电压节点之间。 上拉电路为片上电路（例如I / O缓冲电路或其他合适的电路提供暂时或人造的第二电源电压），例如可能是多电压电源。 在上电期间临时供电电压被提供给片上电路，并且临时隔离电路可操作地隔离可隔离源电压节点，直到第二电源电压达到适当的电平并关断临时隔离电路。

公开(公告)号：US09347836B2

公开(公告)日：2016-05-24

申请号：US13296804

申请日：2011-11-15

申请人： Grigori Temkine ,  Filipp Chekmazov ,  Paul Edelshteyn ,  Oleg Drapkin ,  Kristina Au

发明人： Grigori Temkine ,  Filipp Chekmazov ,  Paul Edelshteyn ,  Oleg Drapkin ,  Kristina Au

IPC分类号： G01K7/01 ,  G06F1/20

CPC分类号： G01K7/01 ,  G06F1/206

摘要： A system and method for measuring integrated circuit (IC) temperature. An integrated circuit (IC) includes a thermal sensor and data processing circuitry. The thermal sensor utilizes switched currents provided to a reference diode and a thermal diode. The ratios of the currents provided to each of these diodes may be chosen to provide a given delta value between the resulting sampled diode voltages. At a later time, a different ratio of currents may be provided to each of these diodes to provide a second given delta value between the resulting sampled diode voltages. A differential amplifier within the data processing circuitry may receive the analog sampled voltages and determine the delta values. Other components within the data processing circuitry may at least digitize and store one or both of the delta values. A difference between the digitized delta values may calculated and used to determine an IC temperature digitized code.

摘要翻译： 一种用于测量集成电路（IC）温度的系统和方法。 集成电路（IC）包括热传感器和数据处理电路。 热传感器利用提供给参考二极管和热二极管的开关电流。 可以选择提供给这些二极管中的每一个的电流的比率以在所得到的采样二极管电压之间提供给定的Δ值。 在稍后的时间，可以向这些二极管中的每一个提供不同的电流比，以在得到的采样的二极管电压之间提供第二给定的Δ值。 数据处理电路内的差分放大器可以接收模拟采样电压并确定增量值。 数据处理电路内的其他组件可以至少数字化并存储增量值中的一个或两个。 可以计算数字化增量值之间的差异，并用于确定IC温度数字化代码。

公开(公告)号：US20080284468A1

公开(公告)日：2008-11-20

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑来检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US07239198B1

公开(公告)日：2007-07-03

申请号：US09211469

申请日：1998-12-14

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： G06G7/12

CPC分类号： H03K19/018585 ,  H03K19/00315 ,  H03K19/018528

摘要： An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

摘要翻译： 集成差分接收器包括单个栅极氧化物差分接收器和相关联的可切换电压供应电路。 集成差分接收器确定所需的接收器电源电压，并选择单栅极氧化物差动接收器的电源电压。 当将较低电源电压确定为所需的电源电压时，集成差分接收器自动向单栅极氧化物差动接收器提供电压，其电压高于I / O焊盘电源电压，并高于最大输入信号电压 增加差动接收器的运行速度。 可切换电压供应电路可操作地响应于指示I / O焊盘所需电源电压的控制信号。 在一个实施例中，单栅极氧化物差动接收器和可切换电压供应电路都是单栅极氧化物电路。

公开(公告)号：US07212592B2

公开(公告)日：2007-05-01

申请号：US10151483

申请日：2002-05-20

申请人： Oleg Drapkin ,  Antonio Rinaldi ,  Mikhall Rodionov ,  Grigori Temkine ,  Michael Foxcroft ,  Edward G. Callway

发明人： Oleg Drapkin ,  Antonio Rinaldi ,  Mikhall Rodionov ,  Grigori Temkine ,  Michael Foxcroft ,  Edward G. Callway

IPC分类号： H04L27/08

CPC分类号： H03M1/185 ,  H03G3/001

摘要： A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

摘要翻译： 公开了一种数字可编程增益控制电路及其操作方法。 所述增益控制电路包括具有由多个重叠的离散单调传递函数段表示的放大器结构的可编程增益放大器，其中在所述多个重叠离散单调传递函数段中的一个或多个中发生至少一个非单调性点， 以及增益段转换器电路，其可操作以将单调增益值转换为段码，以匹配可编程增益放大器的非单调特性。 增益放大器的可编程性由粗增益控制电路和精细增益控制电路提供。

公开(公告)号：US06833746B2

公开(公告)日：2004-12-21

申请号：US10123983

申请日：2002-04-16

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03L500

CPC分类号： H03K19/00315

摘要： A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal. The circuit, in effect, shifts the core logic supply voltage up to provide efficient and safe control of single oxide gate output buffer transistor devices, such as p-channel devices.

摘要翻译： 预缓冲器电压电平移位电路包括多电源电压移位电路，其具有耦合以产生到输出缓冲器的预缓冲器输出信号的单个栅极氧化器件。 对于至少多个电源电压中的每一个，预缓冲器输出信号具有在单栅极氧化物器件的正常栅极电压工作电平内的电平。 在一个实施例中，多电源电压电平移位电路包括耦合到第一或第二电源电压中的至少一个的电流镜，并且还使用诸如被配置为二极管的晶体管的非线性器件，其被耦合 到电流镜的输出。 非线性装置被耦合以从信号源接收数字输入信号，例如来自核心逻辑的一部分。 耦合到非线性装置的开关电路基于数字输入信号的电平选择性地激活非线性装置。 实际上，该电路将核心逻辑电源电压移动，以提供对单个氧化物栅极输出缓冲晶体管器件（例如p沟道器件）的有效和安全的控制。