公开(公告)号：US20070134891A1

公开(公告)日：2007-06-14

申请号：US11302770

申请日：2005-12-14

申请人： Olubunmi Adetutu ,  Robert Jones ,  Ted White

发明人： Olubunmi Adetutu ,  Robert Jones ,  Ted White

IPC分类号： H01L21/00

CPC分类号： H01L21/76254 ,  H01L21/02002

摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.

摘要翻译： 具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。 在一个示例中，在施主晶片上形成具有第一表面取向的半导体结构。 具有第二表面取向的半导体结构形成在第二晶片上。 受体开口形成在第二晶片上。 具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。 所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

公开(公告)号：US20070048919A1

公开(公告)日：2007-03-01

申请号：US11209869

申请日：2005-08-23

申请人： Olubunmi Adetutu ,  Mariam Sadaka ,  Ted White ,  Bich-Yen Nguyen

发明人： Olubunmi Adetutu ,  Mariam Sadaka ,  Ted White ,  Bich-Yen Nguyen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

摘要翻译： 半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161） 电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。 通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。

公开(公告)号：US20060084235A1

公开(公告)日：2006-04-20

申请号：US10965964

申请日：2004-10-15

申请人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Alexander Barr ,  Olubunmi Adetutu ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/78618

摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

摘要翻译： 半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。 设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。 源极/漏极结构形成在沟槽内。 源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。 沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。 源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。 两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

公开(公告)号：US20070235807A1

公开(公告)日：2007-10-11

申请号：US11742955

申请日：2007-05-01

申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

公开(公告)号：US20070210314A1

公开(公告)日：2007-09-13

申请号：US11373536

申请日：2006-03-10

申请人： Brian Winstead ,  Ted White ,  Da Zhang

发明人： Brian Winstead ,  Ted White ,  Da Zhang

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

摘要翻译： 一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。 该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。 该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。 该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是 使用第二种材料创建。

公开(公告)号：US20070190745A1

公开(公告)日：2007-08-16

申请号：US11351518

申请日：2006-02-10

申请人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

发明人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  Y10S438/973

摘要： A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

公开(公告)号：US20060228851A1

公开(公告)日：2006-10-12

申请号：US11093801

申请日：2005-03-30

申请人： Mariam Sadaka ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

发明人： Mariam Sadaka ,  Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn Thomas ,  Ted White

IPC分类号： H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

摘要翻译： 根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。 如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

公开(公告)号：US20050181549A1

公开(公告)日：2005-08-18

申请号：US10780143

申请日：2004-02-17

申请人： Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

发明人： Alexander Barr ,  Dejan Jovanovic ,  Bich-Yen Nguyen ,  Mariam Sadaka ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

摘要： A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.

摘要翻译： 第一半导体结构具有硅衬底，在硅上生长的第一硅锗层，第一硅锗层上的第二硅锗层和第二硅锗层上的应变硅层。 第二半导体结构具有硅衬底和绝缘顶层。 第一半导体结构的硅层被结合到绝缘体层以形成第三半导体结构。 切割第二硅锗层以将大部分第一半导体结构与第三半导体结构分离。 去除硅锗层以暴露随后形成晶体管的应变硅层，其后是从第一半导体结构残留的唯一层。 晶体管沿着<100>方向定向并且与第二硅的基底硅层的<100>方向成45度角。

公开(公告)号：US20060094169A1

公开(公告)日：2006-05-04

申请号：US10977423

申请日：2004-10-29

申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

公开(公告)号：US20060068553A1

公开(公告)日：2006-03-30

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam Sadaka ,  Ted White ,  Alexander Barr ,  Venkat Kolagunta ,  Bich-Yen Nguyen ,  Victor Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。