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公开(公告)号：US10185801B2
公开(公告)日：2019-01-22
申请号：US15409152
申请日：2017-01-18
Applicant: Oracle International Corporation
Inventor： Kiran Kishore Vedantam , Aparna Ramachandran , James Ballard , Mark Russell O'brien , Sampanna Prashant Pathak
IPC: G06F17/50
Abstract: A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.
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公开(公告)号：US09773727B2
公开(公告)日：2017-09-26
申请号：US15181795
申请日：2016-06-14
Applicant: Oracle International Corporation
Inventor： Duncan C. Collier , Robert P. Masleid , Aparna Ramachandran , King Yen
IPC: H01L23/522 , H01L23/498 , H01L21/48 , H01L49/02
CPC classification number: H01L23/5223 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L23/498 , H01L23/49816 , H01L23/5226 , H01L23/5286 , H01L28/40 , H01L2224/0401
Abstract: A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power1 (PWR1) bump pad within a PWR1 bump region, a VSS bump pad within a VSS bump region, and a power2 (PWR2) bump pad within a PWR2 bump region. The metal-top layer may also include a PWR1 majority metal-top region. The MFDM may also include a metal-top-1 layer beneath the metal-top layer and including a VSS majority metal-top-1 region, a PWR1 metal-top-1 region, and a PWR2 metal-top-1 region. The MFDM may also include a metal-top-2 layer beneath the metal-top-1 layer and including a PWR2 majority metal-top-2 region, a VSS metal-top-2 region, and a PWR1 metal-top-2 region. The MFDM may also include top-1 VIAs disposed between the metal-top layer and the metal-top-1 layer, and top-2 VIAs disposed between the metal-top-1 layer and the metal-top-2 layer.
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Patent Agency Ranking
公开(公告)号：US20140009219A1
公开(公告)日：2014-01-09
申请号：US14023322
申请日：2013-09-10
Applicant: Oracle International Corporation
Inventor： Aparna Ramachandran , Gary John Formica
IPC: H01L23/528 , H01L23/00
CPC classification number: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/13124 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/00014 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.
Abstract translation: 一种裸片，包括以第一阵列排列并具有第一电压的第一组功率瓦片; 第二组功率瓦片，布置在与第一阵列偏移的第二阵列中并具有第二电压; 由第二组功率瓦片包围并具有第一电压的一组电力网格段; 第一电力轨道通过一组电力网段和第一组电力瓦片; 以及一组通孔，其操作性地连接电力轨道与一组动力网段和第一组多个功率瓦片。
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公开(公告)号：US08547167B2
公开(公告)日：2013-10-01
申请号：US13732048
申请日：2012-12-31
Applicant: Oracle International Corporation
Inventor： Aparna Ramachandran , Gary John Formica
IPC: G05F3/02
CPC classification number: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/13124 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/00014 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.
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公开(公告)号：US20130120054A1
公开(公告)日：2013-05-16
申请号：US13732048
申请日：2012-12-31
Applicant: Oracle International Corporation
Inventor： Aparna Ramachandran , Gary John Formica
IPC: G05F3/02
CPC classification number: H01L23/5286 , H01L24/11 , H01L24/13 , H01L2224/13124 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/00014 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.
Abstract translation: 一种裸片，包括以第一阵列排列并具有第一电压的第一组功率瓦片; 第二组功率瓦片，布置在与第一阵列偏移的第二阵列中并具有第二电压; 由第二组功率瓦片包围并具有第一电压的一组电力网格段; 第一电力轨道通过一组电力网段和第一组电力瓦片; 以及一组通孔，其操作性地连接电力轨道与一组动力网段和第一组多个功率瓦片。
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公开(公告)号：US20180203971A1
公开(公告)日：2018-07-19
申请号：US15409152
申请日：2017-01-18
Applicant: Oracle International Corporation
Inventor： Kiran Kishore Vedantam , Aparna Ramachandran , James Ballard , Mark Russell O'brien , Sampanna Prashant Pathak
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5077 , G06F2217/78
Abstract: A method may include obtaining a design including cells and a power grid. The method may further include dividing the design into tiles, determining a voltage budget for a tile, calculating a voltage drop for each cell of the tile based on determining an activity factor for the cell and a peak current consumed by the cell, determining, for each cell of the tile and based on the power grid, an affected vicinity for the cell including one or more neighboring cells affected by a current drawn on the cell, determining an affected vicinity for the tile based on the affected vicinity for each cell of the subset, calculating a voltage drop for the tile based on the voltage drop for each cell of the affected vicinity for the tile, and detecting a voltage deviation when a difference between the voltage budget and the voltage drop exceeds a threshold.
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公开(公告)号：US20170092579A1
公开(公告)日：2017-03-30
申请号：US15181795
申请日：2016-06-14
Applicant: Oracle International Corporation
Inventor： Duncan C. Collier , Robert P. Masleid , Aparna Ramachandran , King Yen
IPC: H01L23/522 , H01L21/48 , H01L49/02 , H01L23/498
CPC classification number: H01L23/5223 , H01L21/4846 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L23/498 , H01L23/49816 , H01L23/5226 , H01L23/5286 , H01L28/40 , H01L2224/0401
Abstract: A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power1 (PWR1) bump pad within a PWR1 bump region, a VSS bump pad within a VSS bump region, and a power2 (PWR2) bump pad within a PWR2 bump region. The metal-top layer may also include a PWR1 majority metal-top region. The MFDM may also include a metal-top-1 layer beneath the metal-top layer and including a VSS majority metal-top-1 region, a PWR1 metal-top-1 region, and a PWR2 metal-top-1 region. The MFDM may also include a metal-top-2 layer beneath the metal-top-1 layer and including a PWR2 majority metal-top-2 region, a VSS metal-top-2 region, and a PWR1 metal-top-2 region. The MFDM may also include top-1 VIAs disposed between the metal-top layer and the metal-top-1 layer, and top-2 VIAs disposed between the metal-top-1 layer and the metal-top-2 layer.
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