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8 条记录 (耗时 0.021 秒)

    Polarity synchronization method and apparatus for video signals in a computer system
    5.
    发明授权
    Polarity synchronization method and apparatus for video signals in a computer system 失效
    计算机系统中视频信号的极性同步方法和装置

    公开(公告)号：US5859635A

    公开(公告)日：1999-01-12

    申请号：US922524

    申请日：1997-09-03

    申请人： Chia-Lun Hang ,  Jih-Hsien Soong

    发明人： Chia-Lun Hang ,  Jih-Hsien Soong

    IPC分类号： G09G5/12 ,  G09G5/00

    CPC分类号： G09G5/12

    摘要： A method and apparatus for automatically synchronizing the polarity of video signals generated by a graphics controller card to a display monitor is described. The present invention includes hardware circuitry comprising a storage unit, a detection unit, a selection unit that store, detect, and select input video signals, particularly a vertical and a horizontal synchronization signals, with the same or different polarity that are received from the graphics controller to a display monitor. The present invention synchronizes the polarity of input vertical and horizontal synchronization signals from the graphics controller prior to transmitting the sync signals to the display monitor. The detect and selection circuits of the present invention enable polarity of input sync signals to be synchronized without the use of software as practiced in the prior art.

    摘要翻译： 描述了一种用于将由图形控制器卡产生的视频信号的极性自动同步到显示监视器的方法和装置。 本发明包括硬件电路，其包括存储单元，检测单元，选择单元，其存储，检测和选择具有从图形接收的相同或不同极性的输入视频信号，特别是垂直和水平同步信号 控制器到显示器。 本发明在将同步信号发送到显示监视器之前，同步来自图形控制器的输入垂直和水平同步信号的极性。 本发明的检测和选择电路使得输入同步信号的极性能够在不使用现有技术中实现的软件的情况下同步。

    Enhanced texture map data fetching circuit and method
    6.
    发明授权
    Enhanced texture map data fetching circuit and method 失效
    增强纹理贴图数据提取电路和方法

    公开(公告)号：US5831640A

    公开(公告)日：1998-11-03

    申请号：US770453

    申请日：1996-12-20

    申请人： Vincent W. Wang ,  Jih-Hsien Soong ,  Hongjun Shu ,  Tzoyao Chan

    发明人： Vincent W. Wang ,  Jih-Hsien Soong ,  Hongjun Shu ,  Tzoyao Chan

    IPC分类号： G06T1/20 ,  G06F12/08 ,  G06T1/60 ,  G06T15/04 ,  G06T15/10 ,  G06F13/16

    CPC分类号： G06F12/0875 ,  G06T15/04 ,  G06T15/10

    摘要： A circuit and method for increasing the processing efficiency of texture map data requests within a 3D subunit of a computer controlled graphics display system. The 3D graphics display subsystem includes a polygon engine, a texture map engine and a pixel pipeline. The texture map engine contains a texture map data access (TDA) circuit having a cache controller with a computer readable cache memory for containing recently used texture maps stored in (u,v) coordinate space. The cache controller is limited in handling only n cache miss operations simultaneously. In one embodiment, n is 1. The TDA circuit also contains a texture map address (TMA) FIFO memory unit for storing texture map addresses associated with texture data requests that hit or missed in the cache memory unit. Since the cache controller handles up to n misses, the texture engine stalls when the (n+1).sup.th unprocessed texture request miss is encountered. Therefore, the TMA FIFO at any time contains at most n miss addresses therein. Processing efficiency is increased when a miss is encountered but the TMA FIFO contains unprocessed hit addresses. At this time, simultaneously with the cache controller fetching the texture data for the missed address, it can also advantageously: (1) supply data from the cache memory for the previously encountered and stored hit addresses; and (2) accept new hit addresses into the TMA FIFO thereby effectively avoiding a texture engine stall. This is quite unlike the prior art systems which process no hit addresses upon a texture miss but rather stall the texture engine.

    摘要翻译： 一种用于增加计算机控制的图形显示系统的3D子单元内的纹理映射数据请求的处理效率的电路和方法。 3D图形显示子系统包括多边形引擎，纹理映射引擎和像素管道。 纹理映射引擎包含具有高速缓存控制器的纹理映射数据访问（TDA）电路，该缓存控制器具有计算机可读高速缓冲存储器，用于存储存储在（u，v）坐标空间中的最近使用的纹理映射。 缓存控制器在仅处理n个缓存未命中操作的同时受到限制。 在一个实施例中，n为1.TDA电路还包含纹理映射地址（TMA）FIFO存储器单元，用于存储与高速缓冲存储器单元中的命中或错过的纹理数据请求相关联的纹理映射地址。 由于缓存控制器处理多达n个未命中，当遇到第（n + 1）个未处理的纹理请求未命中时，纹理引擎停止。 因此，TMA FIFO在任何时候最多包含n个未命中的地址。 当遇到错过但是TMA FIFO包含未处理的命中地址时，处理效率会提高。 此时，与缓存控制器同时获取遗漏地址的纹理数据，还可以有利地：（1）从高速缓冲存储器提供先前遇到和存储的命中地址的数据; 和（2）接受新的命中地址到TMA FIFO，从而有效地避免纹理引擎失速。 这与现有技术的系统完全不同，这种系统在纹理丢失时不处理命中地址，而是阻止纹理引擎。

    Universal MPEG decoder with scalable picture size
    7.
    发明授权
    Universal MPEG decoder with scalable picture size 失效
    通用MPEG解码器具有可扩展的图像尺寸

    公开(公告)号：US5832120A

    公开(公告)日：1998-11-03

    申请号：US622330

    申请日：1996-03-26

    申请人： Ramaswamy Prabhakar ,  Tzoyao Chan ,  Jih-Hsien Soong

    发明人： Ramaswamy Prabhakar ,  Tzoyao Chan ,  Jih-Hsien Soong

    IPC分类号： H04N7/30 ,  G06T9/00 ,  H03M7/00 ,  H03M7/30 ,  H04N7/26 ,  H04N7/50 ,  G06K9/36 ,  G06K9/46

    CPC分类号： H04N19/59 ,  H04N19/117 ,  H04N19/122 ,  H04N19/176 ,  H04N19/186 ,  H04N19/44 ,  H04N19/48 ,  H04N19/61 ,  H04N19/82

    摘要： A decoder is disclosed for decoding MPEG video bitstreams encoded in any color space encoding format and outputting the decoded video bitstream to different sized windows. Both MPEG decompression and color space decoding and conversion are performed on the bitstreams within the same decoder. The disclosed decoder may be programmed to output the decoded video bitstream in any of three primary color space formats comprising YUV 4:2:0, YUV 4:2:2, and YUV 4:4:4. The decoder may also output the decoded bitstream to different sized windows using Discrete Cosine Transform (DCT) based image resizing.

    摘要翻译： 公开了一种用于解码以任何颜色空间编码格式编码的MPEG视频比特流的解码器，并将解码的视频比特流输出到不同大小的窗口。 对同一解码器内的比特流执行MPEG解压缩和颜色空间解码和转换。 所公开的解码器可以被编程为以包括YUV 4：2：0，YUV 4：2：2和YUV 4：4：4的三种主色空间格式中的任何一种来输出解码的视频比特流。 解码器还可以使用基于离散余弦变换（DCT）的图像调整大小将解码的比特流输出到不同大小的窗口。

    Reset based computer bus identification method and circuit resilient to power transience
    8.
    发明授权
    Reset based computer bus identification method and circuit resilient to power transience 失效
    基于复位的计算机总线识别方法和电路适应电力瞬态

    公开(公告)号：US5608877A

    公开(公告)日：1997-03-04

    申请号：US409243

    申请日：1995-03-24

    申请人： Chih-Ta Sung ,  Tzoyao Chan ,  Jih-Hsien Soong

    发明人： Chih-Ta Sung ,  Tzoyao Chan ,  Jih-Hsien Soong

    IPC分类号： G06F13/40 ,  G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/4068

    摘要： An automatic bus identification circuit is provided in a device to reliably detect system bus type on power up despite fluctuations in supply voltage. A system bus type signal is received over a multi-function input line at a first input and a reset signal received over a set line at a second input. A bus type identification circuitry is provided to latch the system bus type signal upon power up and continuously output this signal as a system bus type identification signal. To prevent the influence of disturbances in the power supply upon power-up, a flip-flip is provided to output a logic signal in response to a system reset signal. The flip-flop is configured with a strong-N type inverter to insure that the flip-flop will be set into a grounded state as power is applied to the circuit, despite the influence of transient power supply voltages.

    摘要翻译： 在设备中提供自动总线识别电路，以尽可能地供电电压波动来可靠地检测上电时的系统总线类型。 系统总线类型信号通过第一输入端的多功能输入线路接收，并在第二输入端通过设定线路接收复位信号。 提供总线类型识别电路，用于在上电时锁存系统总线类型信号，并将该信号连续输出为系统总线类型识别信号。 为了防止上电时电源干扰的影响，提供触发翻转以响应于系统复位信号输出逻辑信号。 触发器配置有强N型反相器，以确保触发器将被设置为接地状态，尽管施加到电路的功率，尽管瞬态电源电压的影响。