公开(公告)号：US12265076B2

公开(公告)日：2025-04-01

申请号：US17891964

申请日：2022-08-19

Applicant: President and Fellows of Harvard College

Inventor： Donhee Ham ,  Wenxuan Wu ,  Jeffrey T. Abbott ,  Henry Julian Hinton ,  Hongkun Park

IPC: B01L3/00 ,  G01N33/487

Abstract: Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

公开(公告)号：US12147888B2

公开(公告)日：2024-11-19

申请号：US17500429

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Changhyun Kim ,  Houk Jang ,  Henry Julian Hinton ,  Hyeonjin Shin ,  Minhyun Lee ,  Donhee Ham

IPC: G06N3/045 ,  G06F18/214 ,  G06T7/11

Abstract: Disclosed is a neural computer including an image sensor capable of controlling a photocurrent. The neural computer according to an embodiment includes a preprocessor configured to receive an image and generate a feature map for the received image; a flattening unit configured to transform the feature map generated by the preprocessor into tabular data to provide data output; and an image classifier configured to classify images received through the preprocessor by using the data output by the flattening unit as an input value. The preprocessor includes an optical signal processor configured to receive the image and generate the feature map.

公开(公告)号：US20230184739A1

公开(公告)日：2023-06-15

申请号：US17891964

申请日：2022-08-19

Applicant: President and Fellows of Harvard College

Inventor： Donhee Ham ,  Wenxuan Wu ,  Jeffrey T. Abbott ,  Henry Julian Hinton ,  Hongkun Park

IPC: G01N33/487 ,  B01L3/00

CPC classification number: G01N33/48728 ,  B01L3/50853 ,  B01L2300/0829 ,  B01L2300/0645 ,  B01L2300/0636

Abstract: Disclosed herein are semiconductor devices to provide a CMOS-compatible, wafer-scale, multi-well platform that can be used for biomedical or other applications, and methods to operate the same. In some embodiments, circuitry is provided underneath a multiple-well array to electrically interface with electrodes in the wells. To interface with electrodes in a large array, circuitry may be fabricated on a single silicon (Si) wafer having a dimension that is at least the same or larger than that of the multiple-well array. According to one aspect of the present disclosure, standard CMOS fabrication process such as those known to be used in a standard semiconductor foundry may be used without expensive customization for complex fabrication procedures. This may help the production cost to be lowered in some cases.

公开(公告)号：US11374171B2

公开(公告)日：2022-06-28

申请号：US16823865

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Dovran Amanov ,  Renjing Xu ,  Houk Jang ,  Haeryong Kim ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Donhee Ham

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US20250067705A1

公开(公告)日：2025-02-27

申请号：US18294759

申请日：2022-06-13

Applicant: President and Fellows of Harvard College

Inventor： Donhee Ham ,  Young-Ha Hwang ,  Henry Julian Hinton ,  Han Sae Jung ,  Woo-Bin Jung

IPC: G01N27/416

Abstract: An electrochemical apparatus includes an array of pixels disposed on a chip, stimulator circuitry disposed on the chip and configured to provide electrical input signals to cause stimulation of the pixels of the array, and sensor circuitry disposed on the chip and configured to read electrical output signals from the pixels of the array. The stimulator circuitry is configured to provide the input signals to cause stimulation of the pixels individually, and the sensor circuitry is configured to selectively read the output signals from the pixels while the pixels are being stimulated. The sensor circuitry is configured to measure an open-circuit voltage at each of the pixels and a current flow at each of the pixels while the pixels are being stimulated by the stimulator circuitry. The open-circuit voltage may be measured while the current flow is being measured.

公开(公告)号：US20240325731A1

公开(公告)日：2024-10-03

申请号：US18501690

申请日：2023-11-03

Applicant: President and Fellows of Harvard College

Inventor： Hongkun Park ,  Donhee Ham ,  Jeffrey T. Abbott ,  Ling Qin ,  Marsela Jorgolli ,  Tianyang Ye

IPC: A61N1/05 ,  A61N1/06 ,  B82Y5/00 ,  H01L23/48 ,  H01L23/49 ,  H01L29/06

CPC classification number: A61N1/0531 ,  A61N1/05 ,  A61N1/0536 ,  A61N1/06 ,  B82Y5/00 ,  H01L23/48 ,  H01L23/49 ,  H01L29/0676 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/14

Abstract: The present invention generally relates to nanowires. In one aspect, the present invention is generally directed to systems and methods of individually addressing nanowires on a surface, e.g., that are substantially upstanding or vertically-oriented with respect to the surface. In some cases, one or more nanowires may be individually addressed using various integrated circuit (“IC”) technologies, such as CMOS. For example, the nanowires may form an array on top of an active CMOs integrated circuit.

公开(公告)号：US20240219370A1

公开(公告)日：2024-07-04

申请号：US18365172

申请日：2023-08-03

Applicant: President and Fellows of Harvard College

Inventor： Donhee Ham ,  Jeffrey T. Abbott ,  Hongkun Park ,  Wenxuan Wu

IPC: G01N33/487 ,  A61B5/053 ,  A61B5/24 ,  A61N1/18 ,  B82Y15/00 ,  C12M1/42 ,  C12N13/00 ,  G01N27/00

CPC classification number: G01N33/48728 ,  A61B5/053 ,  A61B5/24 ,  A61N1/18 ,  C12M35/02 ,  C12N13/00 ,  G01N27/00 ,  A61B2562/0285 ,  B82Y15/00

Abstract: Methods and systems for stimulating and monitoring electrogenic cells are described. Some systems for stimulating electrogenic cells are based on the injection of electric currents into the cells via electrodes connected to the cells. Such stimulators may comprise an impedance element having an input terminal and an output terminal coupled to an electrode, and a voltage follower coupled between the input terminal and the output terminal of the impedance element, the voltage follower being configured to maintain a substantially constant voltage between the input terminal and the output terminal of the impedance element. The impedance element may comprise one or more switched capacitors at least in some embodiments. In some embodiments, the voltage follower may be implemented using a source follower.

公开(公告)号：US11985910B2

公开(公告)日：2024-05-14

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Dovran Amanov ,  Renjing Xu ,  Houk Jang ,  Haeryong Kim ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Donhee Ham

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/80 ,  H10N70/24 ,  H10N70/8416

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US20230056865A1

公开(公告)日：2023-02-23

申请号：US17869940

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  President and Fellows of Harvard College

Inventor： Seijoon Kim ,  Renjing Xu ,  Hongkun Park ,  Donhee Ham ,  SANG JOON KIM

IPC: G06N3/06

Abstract: A method and apparatus with artificial network generation and/or implementation corresponding to a natural neural network are disclosed. The method includes performing an adjusting, based on a firing time difference between an action potential (AP) of a first biological neuron and a post-synaptic potential (PSP) of a second biological neuron, of a first conductance value of a first memory corresponding to the first and second biological neurons, adjusting the firing time difference based on the PSP of the second biological neuron, and performing another adjusting, by controlling another firing time difference between the AP of the first biological neuron and the PSP of the second biological neuron to be the adjusted firing time difference, of a second conductance value of the first memory corresponding to the first and second biological neurons.

公开(公告)号：US12268106B2

公开(公告)日：2025-04-01

申请号：US18167354

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Houk Jang ,  Donhee Ham ,  Chengye Liu ,  Henry Hinton ,  Haeryong Kim ,  Hyeonjin Shin

IPC: H10N70/00 ,  H10B63/00

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.