公开(公告)号：US11595038B2

公开(公告)日：2023-02-28

申请号：US17256642

申请日：2019-06-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke Kinoshita ,  Yasuhiro Yamada ,  Hidekazu Umeda

IPC: H03K17/56 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H02M7/537

Abstract: A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

公开(公告)号：US09484342B2

公开(公告)日：2016-11-01

申请号：US14938803

申请日：2015-11-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroyuki Handa ,  Hidekazu Umeda ,  Satoshi Tamura ,  Tetsuzo Ueda

IPC: H01L27/06 ,  H01L23/535 ,  H01L29/778 ,  H01L29/861 ,  H01L29/872 ,  H01L29/205 ,  H01L27/095 ,  H01L29/417 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0635 ,  H01L27/095 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Abstract translation: 一种半导体装置，包括：基板; 形成在所述基板上的氮化物半导体层; 形成在所述氮化物半导体层上的晶体管，并且包括依次设置的源电极，栅极电极和漏极电极; 以及形成在氮化物半导体层上的二极管，并且包括依次设置的阳极电极和阴极电极。 半导体装置具有晶体管/二极管对，其中源电极，栅电极，漏电极，阳极电极和阴极电极依次依次设置，晶体管的漏电极和阳极电极 二极管通过漏极/阳极公共电极布线连接并用作公共电极。

公开(公告)号：US09911843B2

公开(公告)日：2018-03-06

申请号：US14636149

申请日：2015-03-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Kazuhiro Kaibara ,  Satoshi Tamura

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US11699751B2

公开(公告)日：2023-07-11

申请号：US17091302

申请日：2020-11-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Kazuhiro Kaibara ,  Satoshi Tamura

IPC: H01L29/80 ,  H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/41758 ,  H01L29/4236

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US09401403B2

公开(公告)日：2016-07-26

申请号：US14636163

申请日：2015-03-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Masahiro Ishida ,  Tetsuzo Ueda ,  Daisuke Ueda

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/205 ,  H01L29/778 ,  H01L29/86 ,  H01L29/15 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/7786 ,  H01L29/86

Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more.

Abstract translation: 本公开的氮化物半导体结构包括半导体衬底和形成在半导体衬底上并包括多个氮化物半导体层的层。 半导体衬底从其包括多个氮化物半导体层的层的一侧开始依次具有表面区域和内部区域。 表面区域的电阻率为0.1Ωcm以上，内部区域的电阻率为1000Ωcm以上。