公开(公告)号：US20190004554A1

公开(公告)日：2019-01-03

申请号：US16122725

申请日：2018-09-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Reiji MOCHIDA ,  Takashi ONO

IPC: G05F1/575 ,  G11C16/30 ,  G11C16/12

Abstract: A regulator circuit has a first non-operating state, a second non-operating state, and an operating state. The regulator circuit includes: a detection circuit that detects a magnitude of an output voltage of the regulator circuit, and outputs a feedback voltage that indicates a result of the detection to a feedback node; an operational amplifier circuit that compares the voltage of the feedback node with a reference voltage, and outputs a voltage that indicates a result of the comparison; and an output circuit that generates the output voltage according to the voltage output from the operational amplifier circuit. A state of the feedback node is different between the first non-operating state and the second non-operating state, and a transition time required to switch from the second non-operating state to the operating state is shorter than a transition time required to switch from the first non-operating state to the operating state.

公开(公告)号：US20150348626A1

公开(公告)日：2015-12-03

申请号：US14826162

申请日：2015-08-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayoshi NAKAYAMA ,  Kazuyuki KOUNO ,  Reiji MOCHIDA ,  Keita TAKAHASHI

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/14 ,  G11C8/08 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/24 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2029/1202 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233

Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

Abstract translation: 存储器阵列包括以矩阵方式布置的多个存储单元，每个存储单元包括单元晶体管和连接到单元晶体管的端部的可变电阻元件，以及包括MOS晶体管的单元晶体管性能测量单元。 电池晶体管性能测量单元用于稳定电阻值低电阻状态的电阻值和可变电阻元件的高电阻状态，而与单元晶体管的变化无关，从而提高非易失性半导体存储器件的读取特性和可靠性。

公开(公告)号：US20190011944A1

公开(公告)日：2019-01-10

申请号：US16131472

申请日：2018-09-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takashi ONO ,  Reiji MOCHIDA

IPC: G05F1/565 ,  G05F1/59 ,  G05F1/575

CPC classification number: G05F1/565 ,  G05F1/56 ,  G05F1/575 ,  G05F1/59

Abstract: A regulator circuit includes: a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection; an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison; an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit; a current detection circuit that detects a magnitude of the output current; and a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit.