公开(公告)号：US20150311329A1

公开(公告)日：2015-10-29

申请号：US14736665

申请日：2015-06-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SATOSHI NAKAZAWA ,  TETSUZO UEDA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205

CPC classification number: H01L29/7781 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0

Abstract translation: 提供了实现更高电流密度和较低接触电阻之间的兼容性并且表现出优异性能的场效应晶体管（FET）及其制造方法。 FET包括：衬底上方的沟道层; 沟道层上方的InAlN层; 在InAlN层上的In x Al y Ga 1-（x + y）N层，其中0

公开(公告)号：US20150194483A1

公开(公告)日：2015-07-09

申请号：US14663140

申请日：2015-03-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： RYO KAJITANI ,  TETSUZO UEDA ,  YOSHIHARU ANDA ,  NAOHIRO TSURUMI ,  SATOSHI NAKAZAWA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/51 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/0611 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

Abstract translation: 目的是通过减少电流崩溃来实现增益的增加，并减少Cgd和Rg。 根据本发明的半导体器件包括：衬底; 设置在所述基板上并由III族氮化物半导体构成的第一半导体层; 设置在第一半导体层上并由III族氮化物半导体构成的第二半导体层; 设置在所述第二半导体层上的栅电极，源电极和漏电极; 设置在所述第二半导体层上的第一场板电极; 以及设置在第一场极板电极上的第二场极板电极，其中第一场极板电极和第二场极板电极设置在栅电极和漏电极之间。

公开(公告)号：US20230336171A1

公开(公告)日：2023-10-19

申请号：US17998658

申请日：2021-04-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YUSUKE KINOSHITA ,  YUTA NAGATOMI ,  RYOSUKE MAEDA ,  SATOSHI NAKAZAWA

IPC: H03K17/082

CPC classification number: H03K17/0822

Abstract: A power loss of a switching device is suppressed. Circuit for a switching device is used in switching device. Switching device includes first path and second path. First path includes first field effect transistor and first inductor. Second path includes second field effect transistor and second inductor. First path and second path are connected in parallel to power supply. A first maximum current that is a maximum current during conduction of first field effect transistor is smaller than a second maximum current that is a maximum current during conduction of second field effect transistor. Circuit for a switching device includes processing part. Processing part executes a specific operation according to a voltage difference between voltage across first inductor and voltage across second inductor.

公开(公告)号：US20230231018A1

公开(公告)日：2023-07-20

申请号：US18001864

申请日：2021-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YUSUKE KINOSHITA ,  MASANORI NOMURA ,  SATOSHI NAKAZAWA

IPC: H01L29/20 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/7787

Abstract: Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.