公开(公告)号：US08824205B2

公开(公告)日：2014-09-02

申请号：US11279385

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C5/06 ,  G11C7/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C8/14 ,  G11C8/12 ,  G11C7/18 ,  G11C7/12

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

公开(公告)号：US08630115B2

公开(公告)日：2014-01-14

申请号：US13198978

申请日：2011-08-05

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/24 ,  G11C16/08 ,  G11C16/06 ,  G11C16/04 ,  G11C5/06 ,  G11C7/02

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

摘要翻译： 非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。

公开(公告)号：US20110286269A1

公开(公告)日：2011-11-24

申请号：US13198978

申请日：2011-08-05

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/08 ,  H01S4/00

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

摘要翻译： 非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。

公开(公告)号：US07649778B2

公开(公告)日：2010-01-19

申请号：US12409740

申请日：2009-03-24

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/04

CPC分类号： G11C5/066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/0483 ,  G11C16/08 ,  G11C2207/105

摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

摘要翻译： 一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中 为了存储器，提供了多个附加的地址引脚。 该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。 还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

公开(公告)号：US07295472B2

公开(公告)日：2007-11-13

申请号：US11279384

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.

摘要翻译： 非易失性存储器电子器件集成在半导体上，并且是具有NAND型结构的闪存EEPROM类型，包括被划分成扇区的至少一个存储器矩阵，其被单独地擦除并且被组织成行或字线和列或位线 的记忆细胞。 有利地，矩阵可以包括其中行或字线对被电短路并且指代单个偏置端子的逻辑扇区，每对行的相关联的单元的源极端子与相应的源选择线相关联，其指向相应的 偏置端子以及至少一对独立的漏极选择线，行和行中的每一行被设置有金属化分流器以逐行排列组和/或加速相应的偏置的传播时间 逻辑部门。

公开(公告)号：US07274594B2

公开(公告)日：2007-09-25

申请号：US11279378

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.

摘要翻译： 非易失性存储器电子器件集成在具有包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵的架构的半导体上。 矩阵被分成至少具有不同访问速度的第一和第二存储器部分。 第一和第二存储器部分可以共享彼此对应的位线的结构并且逐个地并且被放置在第一和第二部分之间的受控开关电中断。

公开(公告)号：US06967876B2

公开(公告)日：2005-11-22

申请号：US10651019

申请日：2003-08-28

申请人： Paolo Rolandi ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Luigi Pascucci

IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C16/12

CPC分类号： G11C16/12

摘要： A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells. Advantageously according to an embodiment of the invention, the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element comprised in the resistive divider and having a further end connected to the programming voltage reference. In such a way, a voltage value obtained by shunting the programming voltage reference is applied at the first circuit node. The voltage regulator according to embodiments of the invention can be used in two-level contexts and in multilevel contexts, even for parallel programming of several multilevel memory cells.

摘要翻译： 用于控制非易失性存储器单元的编程电压电平的方法包括：提供连接到编程电压参考并有效地产生至少一个编程电压电平的电阻分压器; 并提供由电池电流交叉的参考电池。 有利地，根据本发明的实施例，电池电流被施加到电阻分压器以将编程电压电平与参考单元的固有特征相关联。 非易失性存储单元的编程电压调节器至少包括插入在第一和第二参考电压之间并连接到参考存储器单元的输入级，以及与其输出端相对应的电阻分压器，插入 在编程电压基准和第二参考电压之间，并连接到调节器的至少一个输出端，有效地将编程电压提供给非易失性存储单元。 有利地，根据本发明的实施例，输入级的输出端子与电阻分压器的第一电路节点相对应地连接到电阻分压器中包含的电阻元件的端部，并具有连接到编程的另一端 电压参考。 以这种方式，在第一电路节点处施加通过分流编程电压基准获得的电压值。 根据本发明的实施例的电压调节器可以在两级上下文和多级上下文中使用，甚至可以用于几个多电平存储器单元的并行编程。

公开(公告)号：US08759915B2

公开(公告)日：2014-06-24

申请号：US12293534

申请日：2006-03-20

申请人： Paolo Rolandi ,  Cristiano Calligaro ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Cristiano Calligaro ,  Luigi Pascucci

IPC分类号： H01L21/02

CPC分类号： H01L27/11551 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7832

摘要： Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

摘要翻译： 由半导体材料的第一导电条形成的半导体器件; 半导体材料的控制栅极区域，面对第一导电条的沟道部分，以及布置在第一导电条和控制栅极区域之间的绝缘区域。 第一导电带包括具有第一导电类型的导线和具有彼此相邻并且彼此电接触布置的第二导电类型的控制线，并且导线形成沟道部分，第一导电部分和第二导电 部分布置在通道部分的相对侧上。

公开(公告)号：US20090180328A1

公开(公告)日：2009-07-16

申请号：US12409740

申请日：2009-03-24

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/06

CPC分类号： G11C5/066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/0483 ,  G11C16/08 ,  G11C2207/105

摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

摘要翻译： 一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中 为了存储器，提供了多个附加的地址引脚。 该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。 还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

公开(公告)号：US07397702B2

公开(公告)日：2008-07-08

申请号：US11178240

申请日：2005-07-08

申请人： Paolo Rolandi ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Luigi Pascucci

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5634

摘要： A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.

摘要翻译： 用于多电平存储器单元的读/验电路包括：可选择地连接到具有相应阵列阈值电压的多个阵列单元的读终端; 多个参考单元，具有各自的参考阈值电压; 以及用于检测阵列阈值和参考阈值的多个阈值检测电路。 特别地，读取终端和参考单元各自连接到相应的阈值检测电路。 每个阈值检测电路设置有电阻型的相应检测器元件，其被设置为通过与其相关联的相应阵列单元或参考单元的导通的电流响应来遍历。