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    SELECTABLE DRIVE STRENGTH HIGH FREQUENCY CRYSTAL OSCILLATOR CIRCUIT
    1.
    发明申请
    SELECTABLE DRIVE STRENGTH HIGH FREQUENCY CRYSTAL OSCILLATOR CIRCUIT 审中-公开
    可选驱动强度高频晶振振荡器电路

    公开(公告)号：US20100026403A1

    公开(公告)日：2010-02-04

    申请号：US12181394

    申请日：2008-07-29

    申请人： Parvinder Rana ,  Rajesh Yadav

    发明人： Parvinder Rana ,  Rajesh Yadav

    IPC分类号： H03B5/30 ,  H03B5/32

    CPC分类号： H03B5/366 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2201/031

    摘要： A method, system, and apparatus to a selectable drive strength high frequency crystal oscillator circuit are disclosed. In one embodiment, a system includes a crystal oscillator circuit to generate a signal with a specified frequency value, and a programmable amplifier circuit containing a plurality of programmable inverting amplifiers, and wherein certain ones of a plurality of inverting amplifiers are operated to change a gain and/or a bandwidth of the signal according to the specified frequency value of the crystal oscillator circuit. The system may include further comprising a resistor circuit coupled in parallel to the programmable amplifier circuit to set an operating point of the programmable amplifier circuit.

    摘要翻译： 公开了一种可选择的驱动强度高频晶体振荡器电路的方法，系统和装置。 在一个实施例中，系统包括用于产生具有指定频率值的信号的晶体振荡器电路和包含多个可编程反相放大器的可编程放大器电路，并且其中操作多个反相放大器中的某些以改变增益 和/或根据晶体振荡器电路的规定频率值的信号的带宽。 该系统可以进一步包括与可编程放大器电路并联耦合以设置可编程放大器电路的工作点的电阻器电路。

    Secure and reliable policy enforcement
    2.
    发明授权
    Secure and reliable policy enforcement 有权
    安全可靠的政策执行

    公开(公告)号：US08385331B2

    公开(公告)日：2013-02-26

    申请号：US11537196

    申请日：2006-09-29

    申请人： Michael A. Weintraub ,  David E. Young ,  Nabil Bitar ,  Rajesh Yadav

    发明人： Michael A. Weintraub ,  David E. Young ,  Nabil Bitar ,  Rajesh Yadav

    IPC分类号： H04L12/28 ,  H04L29/06 ,  G06F9/00

    CPC分类号： H04L63/0263

    摘要： A system includes a policy enforcement point that is located within a first network. The policy enforcement point is configured to connect the first network to a second network via a secure connection. The policy enforcement point is configured to receive traffic from a first device via the first network or a second device associated with the second network via the secure connection, determine whether to apply a policy to the received traffic, and discard the received traffic when a policy is determined to apply to the received traffic.

    摘要翻译： 系统包括位于第一网络内的策略执行点。 策略执行点被配置为经由安全连接将第一网络连接到第二网络。 策略执行点被配置为经由第一网络或经由安全连接与第二网络相关联的第二设备接收来自第一设备的流量，确定是否对所接收到的流量应用策略，并且在策略中丢弃所接收的流量 被确定为应用于所接收的流量。

    Fast start-up crystal oscillator
    3.
    发明授权
    Fast start-up crystal oscillator 有权
    快速启动晶体振荡器

    公开(公告)号：US08120439B2

    公开(公告)日：2012-02-21

    申请号：US12540367

    申请日：2009-08-13

    申请人： Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

    发明人： Aatmesh Shrivastava ,  Rajesh Yadav ,  Parvinder Kumar Rana

    IPC分类号： H03B5/32 ,  H03L5/00

    CPC分类号： H03B5/06 ,  H03B2200/0094

    摘要： An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

    摘要翻译： 具有降低启动时间的示例性快速启动晶体振荡器。 示例性振荡器通过增加电路的负电阻来减小启动时间（即，在电源接通之后获得持续的稳定振荡所花费的时间）。 增加负电阻会增加振荡的增长率，从而减少启动时间。 示例性晶体振荡器包括具有负电阻的增益级。 具有并联电容的晶体放置在增益级的反馈环路中。 缓冲器耦合到增益级，使得其阻止晶体分流电容加载增益级，有效地增加增益级的负电阻。 此外，振荡检测和控制电路耦合在晶体和增益级之间。 振荡检测和控制电路在启动期间连接缓冲器，一旦振荡信号达到持续的稳定振荡，就断开缓冲器。

    INTERNET PROTOCOL MULTICAST ON PASSIVE OPTICAL NETWORKS
    4.
    发明申请
    INTERNET PROTOCOL MULTICAST ON PASSIVE OPTICAL NETWORKS 有权
    被动光网络上的互联网协议多媒体

    公开(公告)号：US20110235635A1

    公开(公告)日：2011-09-29

    申请号：US12732448

    申请日：2010-03-26

    申请人： Rajesh Yadav

    发明人： Rajesh Yadav

    IPC分类号： H04L12/56 ,  H04J14/00

    CPC分类号： H04Q11/0067 ,  H04L12/18 ,  H04Q11/0071

    摘要： A method for implementing multicast via a passive optical network (PON) may include receiving Internet group multicast protocol (IGMP) messages from a customer device. Multicast information associated with the IGMP messages is identified, wherein the multicast information includes at least multicast group information and customer identification information. The multicast information is stored in a multicast state table. Downstream layer 2 traffic is received and multicast addressing information is extracted from the layer 2 traffic. It is then determined whether the multicast addressing information matches the multicast group information stored in the multicast state table. The layer 2 traffic is forwarded on at least one PON interface corresponding to the customer identification information that is associated with the stored multicast group information when the multicast addressing information matches the multicast group information stored in the multicast state table.

    摘要翻译： 经由无源光网络（PON）实现组播的方法可以包括从客户设备接收因特网组多播协议（IGMP）消息。 识别与IGMP消息相关联的组播信息，其中多播信息至少包括多播组信息和客户识别信息。 组播信息存储在组播状态表中。 从第2层流量中提取下行流2，并提取组播寻址信息。 然后确定多播寻址信息是否与存储在多播状态表中的多播组信息相匹配。 当多播寻址信息与多播状态表中存储的多播组信息相匹配时，第2层流量在与存储的多播组信息相关联的客户识别信息对应的至少一个PON接口上转发。

    Pulse generation circuits in integrated circuits
    5.
    发明授权
    Pulse generation circuits in integrated circuits 有权
    集成电路中的脉冲发生电路

    公开(公告)号：US08797072B2

    公开(公告)日：2014-08-05

    申请号：US14168307

    申请日：2014-01-30

    申请人： Aatmesh Shrivastava ,  Rajesh Yadav

    发明人： Aatmesh Shrivastava ,  Rajesh Yadav

    IPC分类号： H03L7/06 ,  H03L7/00 ,  H03K17/22 ,  G01R21/00

    CPC分类号： G01R21/00 ,  H03K17/223 ,  H03L7/00

    摘要： Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

    摘要翻译： 公开了包括被配置为产生上电复位（POR）脉冲的电路的集成电路（IC）。 IC包括电源检测电路，其被配置为响应于电源信号从第一电平到第二电平的转变而产生感测信号，以及脉冲发生电路与电源检测电路耦合。 脉冲发生电路被配置为基于感测信号产生阈值持续时间的上电复位（POR）脉冲。 IC还包括与脉冲发生电路耦合以接收POR脉冲的复位产生电路。 复位产生电路被配置为基于POR信号和至少一个控制信号产生复位脉冲，其中复位脉冲被配置为用于执行集成电路的一个或多个元件的复位。

    Bus low voltage differential signaling (BLVDS) circuit
    6.
    发明授权
    Bus low voltage differential signaling (BLVDS) circuit 有权
    总线低压差分信号（BLVDS）电路

    公开(公告)号：US07893720B2

    公开(公告)日：2011-02-22

    申请号：US12505471

    申请日：2009-07-18

    申请人： Rajesh Yadav ,  Vinayak Ashok Ghatawade

    发明人： Rajesh Yadav ,  Vinayak Ashok Ghatawade

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018521 ,  H03K19/018528

    摘要： A differential signaling circuit and a control circuit. The differential signaling circuit includes a first positive driver and a first negative driver. The first negative driver has different impedance than the first positive driver. The first positive driver and the first negative driver together define a first current path between positive and negative power supply terminals. A first output is defined on the first current path intermediate the first positive driver and the first negative driver. The control circuit includes a first driver that drives a transmission line at a first output voltage, a feedback amplifier responsive to the first output voltage to generate a control signal and a metal oxide semiconductor (MOS) driver coupled to the first driver and responsive to the control signal to make impedance of the first driver equivalent to impedance of the transmission line.

    摘要翻译： 差分信号电路和控制电路。 差分信号电路包括第一正驱动器和第一负驱动器。 第一个负极驱动器具有与第一个正极驱动器不同的阻抗。 第一正驱动器和第一负驱动器一起定义正电源端子和负电源端子之间的第一电流路径。 第一输出定义在第一正驱动器和第一负驱动器之间的第一电流通路上。 控制电路包括驱动第一输出电压的传输线的第一驱动器，响应第一输出电压产生控制信号的反馈放大器和耦合到第一驱动器的金属氧化物半导体（MOS）驱动器，并响应于 控制信号使第一驱动器的阻抗等于传输线的阻抗。

    POWER ON RESET GENERATION CIRCUITS IN INTEGRATED CIRCUITS
    8.
    发明申请
    POWER ON RESET GENERATION CIRCUITS IN INTEGRATED CIRCUITS 有权
    集成电路中的电源复位生成电路

    公开(公告)号：US20140035634A1

    公开(公告)日：2014-02-06

    申请号：US13567611

    申请日：2012-08-06

    申请人： Aatmesh Shrivastava ,  Rajesh Yadav

    发明人： Aatmesh Shrivastava ,  Rajesh Yadav

    IPC分类号： H03L7/00

    CPC分类号： G01R21/00 ,  H03K17/223 ,  H03L7/00

    摘要： Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

    摘要翻译： 公开了包括被配置为产生上电复位（POR）脉冲的电路的集成电路（IC）。 IC包括电源检测电路，其被配置为响应于电源信号从第一电平到第二电平的转变而产生感测信号，以及脉冲发生电路与电源检测电路耦合。 脉冲发生电路被配置为基于感测信号产生阈值持续时间的上电复位（POR）脉冲。 IC还包括与脉冲发生电路耦合以接收POR脉冲的复位产生电路。 复位产生电路被配置为基于POR信号和至少一个控制信号产生复位脉冲，其中复位脉冲被配置为用于执行集成电路的一个或多个元件的复位。

    Internet protocol multicast on passive optical networks
    9.
    发明授权
    Internet protocol multicast on passive optical networks 有权
    无源光网络上的互联网协议组播

    公开(公告)号：US08254386B2

    公开(公告)日：2012-08-28

    申请号：US12732448

    申请日：2010-03-26

    申请人： Rajesh Yadav

    发明人： Rajesh Yadav

    IPC分类号： H04L12/28

    CPC分类号： H04Q11/0067 ,  H04L12/18 ,  H04Q11/0071

    摘要： A method for implementing multicast via a passive optical network (PON) may include receiving Internet group multicast protocol (IGMP) messages from a customer device. Multicast information associated with the IGMP messages is identified, wherein the multicast information includes at least multicast group information and customer identification information. The multicast information is stored in a multicast state table. Downstream layer 2 traffic is received and multicast addressing information is extracted from the layer 2 traffic. It is then determined whether the multicast addressing information matches the multicast group information stored in the multicast state table. The layer 2 traffic is forwarded on at least one PON interface corresponding to the customer identification information that is associated with the stored multicast group information when the multicast addressing information matches the multicast group information stored in the multicast state table.

    摘要翻译： 经由无源光网络（PON）实现多播的方法可以包括从客户设备接收因特网组多播协议（IGMP）消息。 识别与IGMP消息相关联的组播信息，其中多播信息至少包括多播组信息和客户识别信息。 组播信息存储在组播状态表中。 从第2层流量中提取下行流2，并提取组播寻址信息。 然后确定多播寻址信息是否与存储在多播状态表中的多播组信息相匹配。 当多播寻址信息与多播状态表中存储的多播组信息相匹配时，第2层流量在与存储的多播组信息相关联的客户识别信息对应的至少一个PON接口上转发。