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公开(公告)号：US20130191698A1
公开(公告)日：2013-07-25
申请号：US13353925
申请日：2012-01-19
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , G06F11/1076 , G06F2211/109 , H03M13/09 , H03M13/19 , H03M13/3715
摘要： Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
摘要翻译： 在包括第一存储器通道，第二存储器通道和纠错码（ECC）逻辑的存储器系统中提供通道标记。 存储器系统被配置为执行一种方法，该方法包括接收将第一信道标记应用于第一存储器信道并确定第一信道标记的优先级的请求。 接收到将第二通道标记应用于第二存储器通道的请求，并且确定第二标记的优先级。 确定第一通道标记的优先级高于第二通道标记的优先级。 第一通道标记被提供给ECC逻辑，同时从ECC逻辑阻止第二通道标记。
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2.发明申请CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS 有权CHANNEL MARKING FOR CHIP MARK OVERFLOW和CALIBRATION ERRORS公开(公告)号：US20120173936A1
公开(公告)日：2012-07-05
申请号：US12981017
申请日：2010-12-29
IPC分类号： G06F11/10
CPC分类号： G11C29/44 , G06F11/1044 , G06F11/1076 , G06F11/30 , G06F2211/1064
摘要： Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.
摘要翻译： 当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。 在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。 响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。
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公开(公告)号：US08793544B2
公开(公告)日：2014-07-29
申请号：US12981017
申请日：2010-12-29
CPC分类号： G11C29/44 , G06F11/1044 , G06F11/1076 , G06F11/30 , G06F2211/1064
摘要： Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.
摘要翻译： 当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。 在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。 响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。
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公开(公告)号：US08782485B2
公开(公告)日：2014-07-15
申请号：US13353925
申请日：2012-01-19
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , G06F11/1076 , G06F2211/109 , H03M13/09 , H03M13/19 , H03M13/3715
摘要： Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
摘要翻译： 在包括第一存储器通道，第二存储器通道和纠错码（ECC）逻辑的存储器系统中提供通道标记。 存储器系统被配置为执行一种方法，该方法包括接收将第一信道标记应用于第一存储器信道并确定第一信道标记的优先级的请求。 接收到将第二通道标记应用于第二存储器通道的请求，并且确定第二标记的优先级。 确定第一通道标记的优先级高于第二通道标记的优先级。 第一通道标记被提供给ECC逻辑，同时从ECC逻辑阻止第二通道标记。
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公开(公告)号：US20130191685A1
公开(公告)日：2013-07-25
申请号：US13353814
申请日：2012-01-19
CPC分类号： G06F11/085 , G06F11/1004 , G06F11/1076 , G06F2211/109
摘要： Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.
摘要翻译： 在包括具有多个存储器件的存储器通道的存储器系统中提供通道标记。 存储器件被布置成第一组存储器件和第二组存储器件。 存储器系统被配置为执行包括确定第一组中多于一个阈值数量的存储器件失败的方法。 错误校正码（ECC）被配置为补偿与存储器通道上的第一组中的存储器件相关联的错误，并且对与存储器通道上的第二组中的存储器件相关联的错误执行错误校正。
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公开(公告)号：US08898511B2
公开(公告)日：2014-11-25
申请号：US12822964
申请日：2010-06-24
申请人： Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens , Lisa C. Gower
发明人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。
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公开(公告)号：US08631271B2
公开(公告)日：2014-01-14
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/00
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式， 存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作， 删除，以响应删除任何陈旧的数据完成。
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8.发明申请CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES 失效在存在的存储器件故障存在的情况下修正存储器件和存储器通道故障公开(公告)号：US20120198309A1
公开(公告)日：2012-08-02
申请号：US13016977
申请日：2011-01-29
CPC分类号： G06F11/10 , H03M13/13 , H03M13/1515 , H03M13/152 , H03M13/19
摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.
摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。
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公开(公告)号：US20110320918A1
公开(公告)日：2011-12-29
申请号：US12822469
申请日：2010-06-24
CPC分类号： G06F11/1044 , G06F11/108 , H03M13/19 , H03M13/2906 , H03M13/3761
摘要： Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.
摘要翻译： 在包括计算机实现的方法的冗余存储器系统中的错误校正和检测，所述方法包括接收包括纠错码（ECC）位的数据，从多个信道接收每个信道包括存储器设备位置处的多个存储器件。 该方法还包括计算数据的综合征; 接收一个频道的频道标识符; 以及从所计算的综合征中去除在所述信道上接收的数据的贡献，所述移除导致频道调整的综合征。 频道调整后的综合征被解码，导致故障存储器件的通道调整的存储器件位置，对应于存储器件位置的通道调整的存储器件位置。
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公开(公告)号：US08271932B2
公开(公告)日：2012-09-18
申请号：US12823010
申请日：2010-06-24
CPC分类号： G06F11/1008 , G06F11/108
摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.
摘要翻译： 一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记 通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。
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