公开(公告)号：US20060181954A1

公开(公告)日：2006-08-17

申请号：US11057281

申请日：2005-02-11

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C2207/2263

摘要： A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.

摘要翻译： 提供了一种将二进制值写入存储单元的电路和方法。 电路包括具有第一漏极，第一漏极和第一栅极的第一场效应晶体管，其可操作地耦合在第一漏极和第一源极之间。 第一漏极可操作地耦合到第一存储器单元。 第一门被配置为接收第一数据信号。 电路还包括第二场效应晶体管，其具有可操作地耦合在第二漏极和第二源之间的第二漏极，第二源极和第二栅极。 漏源可操作地耦合到第一存储单元。 第二门被配置为接收第二数据信号。 电路还包括具有第一输入端和第一输出端的第一信号反相器。 第一输出端子可操作地耦合到第一和第二源两者。 第一信号反相器被配置为当第一输入端子接收到第二控制信号时，在第一输出端子上输出第一控制信号。 当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时，第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值 。

公开(公告)号：US20060181951A1

公开(公告)日：2006-08-17

申请号：US11056048

申请日：2005-02-11

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/16

摘要： A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.

摘要翻译： 一种用于为多端口存储器阵列产生一个或多个公共地址信号的系统。 该系统包括接收一个或多个读取地址信号的电路; 接收一个或多个写入地址信号的电路; 接收阵列时钟信号的电路; 接收一个或多个使能信号的电路; 以及响应于使能信号，阵列时钟信号和读地址信号和写入地址信号之一产生公共地址信号的电路。

公开(公告)号：US20060179382A1

公开(公告)日：2006-08-10

申请号：US11054737

申请日：2005-02-10

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F12/0207 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

摘要： A method and circuit for implementing array bypass operations without access penalty for a random access memory circuit. The random access memory circuit includes a circuit array of memory cells, a read circuit, a data output register, a data input register, a write circuit, a write control register, a bypass control register, a row decoder, and an address register. The method includes directly coupling the read circuit to the data output register and coupling-the bypass control register to the row detector. The bypass control register issues a bypass signal to the row decoder. The bypass signal includes one of an active bypass signal and an inactive bypass signal. If the bypass signal issued is inactive, then one of a read operation and a write-through operation without bypass is performed. If the bypass control signal issued is active, then a write-through operation is performed in bypass mode.

摘要翻译： 一种用于实现阵列旁路操作的方法和电路，对随机存取存储器电路无访问损失。 随机存取存储器电路包括存储单元的电路阵列，读取电路，数据输出寄存器，数据输入寄存器，写入电路，写入控制寄存器，旁路控制寄存器，行解码器和地址寄存器。 该方法包括将读取电路直接耦合到数据输出寄存器，并将旁路控制寄存器耦合到行检测器。 旁路控制寄存器向行解码器发出旁路信号。 旁路信号包括有源旁路信号和不活动旁路信号之一。 如果发出的旁路信号无效，则执行读取操作和无旁路的直写操作之一。 如果发出的旁路控制信号有效，则在旁路模式下执行直通操作。

公开(公告)号：US20050226063A1

公开(公告)日：2005-10-13

申请号：US10814719

申请日：2004-03-31

申请人： Paul Bunce ,  John Davis ,  Thomas Knips ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Thomas Knips ,  Donald Plass

IPC分类号： G11C8/00 ,  G11C29/00

CPC分类号： G11C29/806 ,  G11C29/848

摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.

摘要翻译： 所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。 实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。 为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。 为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。 如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。 然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。 这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。

公开(公告)号：US20060181952A1

公开(公告)日：2006-08-17

申请号：US11056049

申请日：2005-02-11

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/419

摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

摘要翻译： 本发明可以包括当将局部位线连接到全局位线或其他电路时用于可编程控制放电去激活信号的电路。 本发明还可以包括一种用于可编程接地电路控制的方法，用于当通过位线评估放电装置将局部位线连接到全局位线时控制放电信号去激活，包括：向控制器电路的输入提供输入逻辑状态; 从所述控制器电路输出可调节的接地值; 并以可调地面值控制位线评估放电装置。

公开(公告)号：US20060176756A1

公开(公告)日：2006-08-10

申请号：US11054059

申请日：2005-02-09

申请人： John Davis ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

发明人： John Davis ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

公开(公告)号：US20060176743A1

公开(公告)日：2006-08-10

申请号：US11054270

申请日：2005-02-09

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G11C7/10

CPC分类号： G11C7/1048 ,  G11C7/1078 ,  G11C7/1096

摘要： Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed.

摘要翻译： 本发明的实施例包括用于将本地位线与全局位线接口的电路。 该电路包括通过本地位线装置耦合到本地位线的接口线。 全局输出设备具有耦合到接口线的输入和耦合到全局位线的输出。 夹紧装置耦合到接口线，夹紧装置响应于信号中的数据将接口线耦合到地。 还公开了一种具有该电路的存储器。

公开(公告)号：US20070237020A1

公开(公告)日：2007-10-11

申请号：US11762833

申请日：2007-06-14

申请人： John Davis ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

发明人： John Davis ,  Paul Bunce ,  Donald Plass ,  Kenneth Reyer

IPC分类号： G11C8/12

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

公开(公告)号：US20060176760A1

公开(公告)日：2006-08-10

申请号：US11054176

申请日：2005-02-09

申请人： Paul Bunce ,  John Davis ,  James Dawson ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  James Dawson ,  Donald Plass

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供全局和本地读取控制同步方法和系统。 解码地址信号以基于子阵列选择信号和累积子阵列选择信号来激活。 每当子阵列选择信号变为有效时，累积子阵列选择信号变为有效，因此累积子阵列选择信号的每个脉冲与子阵列选择信号的一个脉冲同步。 使用子阵列选择信号获得用于多个存储器子阵列的本地读取控制信号，并且使用累积子阵列选择信号获得用于存储器阵列的至少一个全局读取控制信号。 在一个示例中，存储器阵列具有分层位线架构。

公开(公告)号：US20060176747A1

公开(公告)日：2006-08-10

申请号：US11054296

申请日：2005-02-09

申请人： Paul Bunce ,  John Davis ,  Donald Plass

发明人： Paul Bunce ,  John Davis ,  Donald Plass

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C2207/002

摘要： A circuit for interfacing local bitlines to a global bitline. The circuit includes a first device having an input coupled to a first local bitline in a first memory sub-array. A second device has an input coupled to a second local bitline in a second memory sub-array. An interface line is coupled to an output of the first device and coupled to an output of the second device. A precharge device is coupled to the interface line, the precharge device coupling the interface line to ground in response to a precharge signal. A global output device has an input coupled to the interface line and an output coupled to the global bitline.

摘要翻译： 用于将本地位线连接到全局位线的电路。 电路包括具有耦合到第一存储器子阵列中的第一本地位线的输入的第一器件。 第二设备具有耦合到第二存储器子阵列中的第二本地位线的输入。 接口线耦合到第一设备的输出并耦合到第二设备的输出。 预充电装置耦合到接口线，预充电装置响应于预充电信号将接口线耦合到地。 全局输出设备具有耦合到接口线的输入和耦合到全局位线的输出。