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1.发明授权Event driven interface for a system for monitoring and controlling a data communications network 失效用于监视和控制数据通信网络的系统的事件驱动接口
公开(公告)号：US5365514A
公开(公告)日：1994-11-15
申请号：US24575
申请日：1993-03-01
CPC分类号： H04L43/00 , H04L12/2602
摘要： An Event Driven Interface (EDI) is disclosed for use as a subsystem of a monitoring and control system for a data communications network. The network communicates a serial stream of binary bits having a characteristic pattern. The system includes a control vector generator for generating a control vector C(i) which describes the characteristic pattern and an event vector analyzer for analyzing an event vector E(i) which represents a plurality of occurrences of the pattern on the network.
摘要翻译： 事件驱动接口（EDI）被公开用作数据通信网络的监视和控制系统的子系统。 网络传送具有特征图案的二进制位串行流。 该系统包括用于生成描述特征模式的控制向量C（i）的控制向量生成器和用于分析表示网络上的模式的多次出现的事件向量E（i）的事件向量分析器。
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2.发明授权Information collection architecture and method for a data communications network 失效用于数据通信网络的信息收集架构和方法
公开(公告)号：US5375070A
公开(公告)日：1994-12-20
申请号：US24572
申请日：1993-03-01
CPC分类号： H04L43/06 , H04L41/142
摘要： A system and process are disclosed that allows the collection of events to be organized and ordered so that relationship between events and the events themselves can be identified as a state or series of states which describe and allow control of performance aspects of protocol activity. The architecture allows dynamic programming of multiple of devices for the purposes of coordination and correlation of events such that monitoring, performance analysis and control can be accomplished on a real-time basis for any speed network. The architecture facilitates feedback of the correlated events for the purposes of monitoring and controlling network activity.
摘要翻译： 公开了一种系统和过程，其允许事件的收集被组织和排序，使得事件和事件本身之间的关系可以被识别为描述和允许控制协议活动的性能方面的状态或一系列状态。 该架构允许多个设备的动态编程，用于协调和关联事件的目的，使得可以实时地为任何速度网络完成监控，性能分析和控制。 该架构有助于相关事件的反馈，以便监控和控制网络活动。
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3.发明申请公开(公告)号：US20080162998A1
公开(公告)日：2008-07-03
申请号：US12048284
申请日：2008-03-14
IPC分类号： G06F11/00
摘要： A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M−1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.
摘要翻译： 测试模式被加载到驱动器数据移位寄存器中，并通过M位总线（0到M-1）从驱动器芯片发送到接收芯片。 测试模式也在接收芯片处产生，用于与实际接收的数据进行比较。 失败的比较被存储为位错误寄存器（BER）中的逻辑比较。 计数器通过从BER计数逻辑值来确定故障次数。 错误位置计数器的内容被锁存在错误位置锁存器中，用于将逻辑1（在错误位位置）加载到接收器芯片和驱动器芯片中的菊花链自愈控制寄存器（SCR）中。 在错误位隔离故障位路径并添加位位置M中的备用位路径之后，SCR将逻辑1设置为所有位位置。
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4.发明授权公开(公告)号：US07330479B2
公开(公告)日：2008-02-12
申请号：US10670711
申请日：2003-09-25
申请人： Kenneth J. Barker , Chad B. McBride
发明人： Kenneth J. Barker , Chad B. McBride
CPC分类号： H04L49/103 , H04L49/254
摘要： In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种用于控制第一和第二时钟域之间的数据流的第一方法。 第一种方法包括以下步骤：（1）选择包含在发送数据的第二时钟域中的物理层接口中的多个端口中的一个; 以及（2）将数据从第一时钟域中的发送缓冲器发送到第二时钟域中物理层接口中的选定端口。 提供了许多其他方面。
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5.发明授权Coupling apparatus and method for increasing the connection capability of a communication system 失效一种用于增加通信系统的连接能力的耦合装置和方法
公开(公告)号：US5432910A
公开(公告)日：1995-07-11
申请号：US909884
申请日：1992-07-07
申请人： Kenneth J. Barker , George M. Calhoun , Jean Calvignac , Rene Castel , Jean C. Dispensa , Yves Huchet , Edward S. Suffern , Ruggero Ulivastro
发明人： Kenneth J. Barker , George M. Calhoun , Jean Calvignac , Rene Castel , Jean C. Dispensa , Yves Huchet , Edward S. Suffern , Ruggero Ulivastro
CPC分类号： G06F13/128 , G06F13/124
摘要： The connection capability of a communication controller is extended. The communication controller includes a central control unit CCU, running a network control program NCP stored in a memory having a direct memory access facility through a DMA bus. The input/output bus of the communication controller and DMA bus are connected to line adapters, and channel adapters and a controller extension through a coupler which allows additional adapters to be connected to the controller. At initialization, a table is built into a coupler memory, which is then used in steady state mode for controlling the transmission of the messages to the additional users and the reception of the messages from the additional users, by improving the buffer unchaining and chaining processes into the NCP memory.
摘要翻译： 通信控制器的连接能力得到延长。 通信控制器包括中央控制单元CCU，其通过DMA总线运行存储在具有直接存储器访问设施的存储器中的网络控制程序NCP。 通信控制器和DMA总线的输入/输出总线通过耦合器连接到线路适配器，通道适配器和控制器扩展，允许其他适配器连接到控制器。 在初始化时，一个表被内置到一个耦合器存储器中，然后在稳态模式下使用这种方式，通过改进缓冲器解链和链接过程来控制消息到附加用户的传输和来自附加用户的消息的接收 进入NCP内存。
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6.发明授权
公开(公告)号：US5606559A
公开(公告)日：1997-02-25
申请号：US515183
申请日：1995-08-11
申请人： Ryan L. Badger , Kenneth J. Barker , Paul H. Nichols , Russell E. Schroter , John K. Stacy , Mark C. Wartski
发明人： Ryan L. Badger , Kenneth J. Barker , Paul H. Nichols , Russell E. Schroter , John K. Stacy , Mark C. Wartski
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L2012/5681
摘要： An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list. A receive ready list is established by the device driver in system memory with the location indicated to the adapter via the receive control registers in the adapter. The receive data cells are reassembled into frames in buffers from the free buffer list. At completion of a received frame, the frame is added to an appropriate receive ready list. An interrupt is generated to the processor by the adapter when one or more completed frames reside on the receive ready list for transmission to the network.
摘要翻译： ATM通信网络包括具有设备驱动器和耦合到接口处的适配器的存储器的系统处理器。 存储在存储器中的帧使用驻留在适配器中并由发送控制寄存器定义的发送就绪队列发送到网络。 这些帧通过描述符和指针链接在一起，以接收由设备驱动程序维护的准备好的列表。 使用发送控制寄存器在系统存储器中建立发送帧完整列表。 适配器产生中断，指示何时帧传输完成。 同时，根据由设备驱动程序建立的空闲缓冲器列表，从网络接收单元并将其存储在系统存储器中。 指针由设备驱动程序维护到接收空闲缓冲区列表的最后一个条目。 适配器维护指向要从接收空闲缓冲区列表中使用的下一个缓冲区的指针。 系统存储器中的设备驱动程序建立接收就绪列表，并通过适配器中的接收控制寄存器向适配器指示位置。 接收数据单元从缓冲区列表中重新组装成缓冲区中的帧。 在完成接收到的帧时，帧被添加到适当的接收就绪列表。 当一个或多个完成的帧驻留在接收就绪列表上以传输到网络时，由适配器向处理器产生中断。
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公开(公告)号：US4809155A
公开(公告)日：1989-02-28
申请号：US33388
申请日：1987-04-02
CPC分类号： G06F13/128 , G06F13/124
摘要： The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48).The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter.The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.
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