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    Variable gain selection in direct conversion receiver
    1.
    发明授权
    Variable gain selection in direct conversion receiver 失效
    直接转换接收机中的可变增益选择

    公开(公告)号：US07076225B2

    公开(公告)日：2006-07-11

    申请号：US10034734

    申请日：2001-12-21

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    IPC分类号： H04B7/00

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Direct conversion receiver architecture
    2.
    发明授权
    Direct conversion receiver architecture 有权
    直接转换接收机架构

    公开(公告)号：US08626099B2

    公开(公告)日：2014-01-07

    申请号：US11376502

    申请日：2006-03-14

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    IPC分类号： H04B1/06

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Direct conversion receiver architecture with digital fine resolution variable gain amplification
    4.
    发明授权
    Direct conversion receiver architecture with digital fine resolution variable gain amplification 有权
    直接转换接收机架构，具有数字精细分辨率可变增益放大

    公开(公告)号：US08634790B2

    公开(公告)日：2014-01-21

    申请号：US11131147

    申请日：2005-05-16

    申请人： Paul E. Peterzell ,  Christian Holenstein ,  Inyup Kang ,  Tao Li ,  Matthew L. Severson

    发明人： Paul E. Peterzell ,  Christian Holenstein ,  Inyup Kang ,  Tao Li ,  Matthew L. Severson

    IPC分类号： H04B1/06 ,  H04B7/00

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Direct conversion receiver architecture
    5.
    发明申请
    Direct conversion receiver architecture 有权
    直接转换接收机架构

    公开(公告)号：US20110105070A1

    公开(公告)日：2011-05-05

    申请号：US11376502

    申请日：2006-03-14

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    IPC分类号： H03L5/00 ,  H04B1/16

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    DIRECT CONVERSION RECEIVER ARCHITECTURE
    6.
    发明申请
    DIRECT CONVERSION RECEIVER ARCHITECTURE 有权
    直接转换接收机架构

    公开(公告)号：US20080014895A1

    公开(公告)日：2008-01-17

    申请号：US11862330

    申请日：2007-09-27

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett Walker ,  Paul Peterzell ,  Raghu Challa ,  Matthew Severson ,  Arun Raghupathy ,  Gilbert Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett Walker ,  Paul Peterzell ,  Raghu Challa ,  Matthew Severson ,  Arun Raghupathy ,  Gilbert Sih

    IPC分类号： H04B1/26

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Direct conversion receiver architecture
    7.
    发明申请
    Direct conversion receiver architecture 有权
    直接转换接收机架构

    公开(公告)号：US20050208916A1

    公开(公告)日：2005-09-22

    申请号：US11131147

    申请日：2005-05-16

    申请人： Paul Peterzell ,  Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    发明人： Paul Peterzell ,  Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    IPC分类号： H03G1/00 ,  H03G3/20 ,  H03G3/30 ,  H04L27/22 ,  H04L27/38 ,  H04B1/06 ,  H04B1/26 ,  H04B7/00

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Direct current offset cancellation for mobile station modems using direct conversion
    8.
    发明授权
    Direct current offset cancellation for mobile station modems using direct conversion 失效

    公开(公告)号：US06985711B2

    公开(公告)日：2006-01-10

    申请号：US10139205

    申请日：2002-05-02

    申请人： Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    发明人： Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    IPC分类号： H04B1/10

    CPC分类号： H04L25/061 ,  H04B1/30

    摘要： A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.