公开(公告)号：US08874065B2

公开(公告)日：2014-10-28

申请号：US12575695

申请日：2009-10-08

申请人： Chengzhi Pan ,  Joseph Patrick Burke ,  Christian Holenstein

发明人： Chengzhi Pan ,  Joseph Patrick Burke ,  Christian Holenstein

IPC分类号： H04B1/16 ,  H04W52/02 ,  H04W48/16

CPC分类号： H04W52/02 ,  H04W48/16 ,  H04W52/0209 ,  H04W52/0235 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/22 ,  Y02D70/23

摘要： The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

摘要翻译： 所描述的装置和方法可以包括被配置为接收控制信号的接收机，以及控制器，其被配置为基于控制信号来调节在小于一个无线电帧的间隔期间接收机的功率消耗。 控制器还可以被配置为基于控制信号在小于一个无线电帧的间隔期间调节发射机的功率消耗。

公开(公告)号：US20100198898A1

公开(公告)日：2010-08-05

申请号：US12366363

申请日：2009-02-05

申请人： Chengzhi Pan ,  Joseph P. Burke

发明人： Chengzhi Pan ,  Joseph P. Burke

IPC分类号： G06F17/17 ,  G06F17/10

CPC分类号： H03H17/0248 ,  H03H15/023 ,  H03H19/004 ,  H03H2007/0192

摘要： Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

摘要翻译： 本文描述了无源开关电容器（PSC）滤波器。 在一个设计中，PSC滤波器实现具有两个复杂的一阶IIR部分的二阶无限脉冲响应（IIR）滤波器。 每个复杂的一阶IIR部分包括三组电容器。 第一组电容器接收实际输入信号和虚拟延迟信号，存储和共享电荷，并提供实际滤波信号。 第二组电容器接收虚拟输入信号和实际延迟信号，存储和共享电荷，并提供虚数滤波信号。 第三组电容器接收实际和虚拟滤波信号，存储和共享电荷，并提供实时和虚拟延迟信号。 在另一种设计中，PSC滤波器实现复杂一阶IIR部分的有限脉冲响应（FIR）部分和IIR部分。 IIR部分包括以交错方式操作的多个复杂滤波器部分。

公开(公告)号：US20080278837A1

公开(公告)日：2008-11-13

申请号：US12178426

申请日：2008-07-23

申请人： Chengzhi Pan ,  Andrei Vityaev

发明人： Chengzhi Pan ,  Andrei Vityaev

IPC分类号： G11B20/10

CPC分类号： G11B20/10027 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B27/3027

摘要： One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

摘要翻译： 呈现一个或多个方法和系统，用于执行从硬盘驱动器的一个或多个数据扇区读取的数据的增益和定时获取。 增益和定时信息可用于将硬盘驱动器的读通道接收器与从数据扇区读取的数据同步。 在代表性实施例中，一个或多个方法包括使用驻留在硬盘驱动器中的一个或多个数据扇区的一个或多个前导码来确定一个或多个频率和相位偏移。 在代表性实施例中，可以确定一个或多个前导码的增益。 在另一代表性实施例中，用于确定一个或多个相位和频率偏移以及振幅的一个或多个系统包括能够利用由一个或多个数据扇区的一个或多个前导码提供的连续样本序列的硬件和/或软件 。

公开(公告)号：US07405894B2

公开(公告)日：2008-07-29

申请号：US10887544

申请日：2004-07-08

申请人： Chengzhi Pan ,  Andrei Vityaev

发明人： Chengzhi Pan ,  Andrei Vityaev

IPC分类号： G11B5/09

CPC分类号： G11B20/10027 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B27/3027

摘要： One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

摘要翻译： 呈现一个或多个方法和系统，用于执行从硬盘驱动器的一个或多个数据扇区读取的数据的增益和定时获取。 增益和定时信息可用于将硬盘驱动器的读通道接收器与从数据扇区读取的数据同步。 在代表性实施例中，一个或多个方法包括使用驻留在硬盘驱动器中的一个或多个数据扇区的一个或多个前导码来确定一个或多个频率和相位偏移。 在代表性实施例中，可以确定一个或多个前导码的增益。 在另一代表性实施例中，用于确定一个或多个相位和频率偏移以及振幅的一个或多个系统包括能够利用由一个或多个数据扇区的一个或多个前导码提供的连续样本序列的硬件和/或软件 。

公开(公告)号：US08768997B2

公开(公告)日：2014-07-01

申请号：US12366363

申请日：2009-02-05

申请人： Chengzhi Pan ,  Joseph Burke

发明人： Chengzhi Pan ,  Joseph Burke

IPC分类号： G06G7/02

CPC分类号： H03H17/0248 ,  H03H15/023 ,  H03H19/004 ,  H03H2007/0192

摘要： Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

摘要翻译： 本文描述了无源开关电容器（PSC）滤波器。 在一个设计中，PSC滤波器实现具有两个复杂的一阶IIR部分的二阶无限脉冲响应（IIR）滤波器。 每个复杂的一阶IIR部分包括三组电容器。 第一组电容器接收实际输入信号和虚拟延迟信号，存储和共享电荷，并提供实际滤波信号。 第二组电容器接收虚拟输入信号和实际延迟信号，存储和共享电荷，并提供虚数滤波信号。 第三组电容器接收实际和虚拟滤波信号，存储和共享电荷，并提供实时和虚拟延迟信号。 在另一种设计中，PSC滤波器实现复杂一阶IIR部分的有限脉冲响应（FIR）部分和IIR部分。 IIR部分包括以交错方式操作的多个复杂滤波器部分。

公开(公告)号：US20100237710A1

公开(公告)日：2010-09-23

申请号：US12408558

申请日：2009-03-20

申请人： Russell John Fagg ,  Chengzhi Pan

发明人： Russell John Fagg ,  Chengzhi Pan

IPC分类号： H02M3/18

CPC分类号： H02M3/07 ,  H03F3/005 ,  H03F3/45475

摘要： Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

摘要翻译： 用于在第一和第二输出电压之间产生差分输出电压的技术，其是第一和第二输入电压之间的差分输入电压的两倍。 在一个方面，构成倍压器的第一和第二电容器在充电阶段被充电到差分输入电压。 在与充电阶段的时间不重叠的输出阶段期间，第一和第二电容器被串联堆叠以产生差分输出电压。 第一和第二电容器都耦合到单个共模电压以提供预定的共模输出电压。 描述了用于提供两个或多个组成电压倍增器以延长输出相位的进一步的技术。

公开(公告)号：US20060007571A1

公开(公告)日：2006-01-12

申请号：US10887544

申请日：2004-07-08

申请人： Chengzhi Pan ,  Andrei Vityaev

发明人： Chengzhi Pan ,  Andrei Vityaev

IPC分类号： G11B5/09

CPC分类号： G11B20/10027 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B27/3027

摘要： One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

摘要翻译： 呈现一个或多个方法和系统，用于执行从硬盘驱动器的一个或多个数据扇区读取的数据的增益和定时获取。 增益和定时信息可用于将硬盘驱动器的读通道接收器与从数据扇区读取的数据同步。 在代表性实施例中，一个或多个方法包括使用驻留在硬盘驱动器中的一个或多个数据扇区的一个或多个前导码来确定一个或多个频率和相位偏移。 在代表性实施例中，可以确定一个或多个前导码的增益。 在另一代表性实施例中，用于确定一个或多个相位和频率偏移以及振幅的一个或多个系统包括能够利用由一个或多个数据扇区的一个或多个前导码提供的连续样本序列的硬件和/或软件 。

公开(公告)号：US08437299B2

公开(公告)日：2013-05-07

申请号：US12857729

申请日：2010-08-17

申请人： Chengzhi Pan ,  Joseph P. Burke

发明人： Chengzhi Pan ,  Joseph P. Burke

IPC分类号： H04J3/00 ,  H04W4/00

CPC分类号： H03M3/47

摘要： Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter. In another example, the de-aggregator involves a decoder and the aggregator involves a precoder.

摘要翻译： 来自多个电路路径的多个流是块TDM（块分时复用），被聚合成单个流，该流通过单个路径通过能够处理聚合信号的处理电路。 避免了提供冗余处理电路的成本。 在单路径处理之后，所得到的信号被阻塞TDM去聚合以产生多个流。 每个输出流基本上与使用单独的处理电路在单独路径中处理相应的输入流时基本相同。 路径共享技术可用于通过一个上级Delta-Sigma ADC（DSADC）从多个无线电接收机传递多个流，而不是使用多个平面ADC来处理来自多个接收器的信息。 在一个示例中，可以使用DSADC，因为聚合是基于Block-TDM的，并且去聚合器涉及数字低通滤波器。 在另一示例中，解聚集器涉及解码器，并且聚合器涉及预编码器。

公开(公告)号：US08274179B2

公开(公告)日：2012-09-25

申请号：US12408558

申请日：2009-03-20

申请人： Russell John Fagg ,  Chengzhi Pan

发明人： Russell John Fagg ,  Chengzhi Pan

IPC分类号： H02M3/18

CPC分类号： H02M3/07 ,  H03F3/005 ,  H03F3/45475

摘要： Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

摘要翻译： 用于在第一和第二输出电压之间产生差分输出电压的技术，其是第一和第二输入电压之间的差分输入电压的两倍。 在一个方面，构成倍压器的第一和第二电容器在充电阶段被充电到差分输入电压。 在与充电阶段的时间不重叠的输出阶段期间，第一和第二电容器被串联堆叠以产生差分输出电压。 第一和第二电容器都耦合到单个共模电压以提供预定的共模输出电压。 描述了用于提供两个或多个组成电压倍增器以延长输出相位的进一步的技术。

公开(公告)号：US20120044927A1

公开(公告)日：2012-02-23

申请号：US12857729

申请日：2010-08-17

申请人： Chengzhi Pan ,  Joseph P. Burke

发明人： Chengzhi Pan ,  Joseph P. Burke

IPC分类号： H04J3/00

CPC分类号： H03M3/47

摘要： Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter. In another example, the de-aggregator involves a decoder and the aggregator involves a precoder.

摘要翻译： 来自多个电路路径的多个流是块TDM（块分时复用），被聚合成单个流，该流通过单个路径通过能够处理聚合信号的处理电路。 避免了提供冗余处理电路的成本。 在单路径处理之后，所得到的信号被阻塞TDM去聚合以产生多个流。 每个输出流基本上与使用单独的处理电路在单独路径中处理相应的输入流时基本相同。 路径共享技术可用于通过一个上级Delta-Sigma ADC（DSADC）从多个无线电接收机传递多个流，而不是使用多个平面ADC来处理来自多个接收器的信息。 在一个示例中，可以使用DSADC，因为聚合是基于Block-TDM的，并且去聚合器涉及数字低通滤波器。 在另一示例中，解聚集器涉及解码器，并且聚合器涉及预编码器。