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    DIRECT CONVERSION RECEIVER ARCHITECTURE
    2.
    发明申请
    DIRECT CONVERSION RECEIVER ARCHITECTURE 有权
    直接转换接收机架构

    公开(公告)号：US20080014895A1

    公开(公告)日：2008-01-17

    申请号：US11862330

    申请日：2007-09-27

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett Walker ,  Paul Peterzell ,  Raghu Challa ,  Matthew Severson ,  Arun Raghupathy ,  Gilbert Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett Walker ,  Paul Peterzell ,  Raghu Challa ,  Matthew Severson ,  Arun Raghupathy ,  Gilbert Sih

    IPC分类号： H04B1/26

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    METHODS AND APPARATUS FOR IMPLEMENTING PHASE ROTATION AT BASEBAND FREQUENCY FOR TRANSMIT DIVERSITY
    5.
    发明申请
    METHODS AND APPARATUS FOR IMPLEMENTING PHASE ROTATION AT BASEBAND FREQUENCY FOR TRANSMIT DIVERSITY 有权
    用于实施基带频率的发射多径相位旋转的方法和装置

    公开(公告)号：US20100029223A1

    公开(公告)日：2010-02-04

    申请号：US12185041

    申请日：2008-08-01

    申请人： Yiwu Tang ,  Christian Holenstein ,  Marco Cassia ,  Mahim Ranjan

    发明人： Yiwu Tang ,  Christian Holenstein ,  Marco Cassia ,  Mahim Ranjan

    IPC分类号： H04B7/02

    CPC分类号： H04B7/0682 ,  H04L1/0618 ,  H04L1/08

    摘要： An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path may perform phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal.

    摘要翻译： 用于实现用于发射分集的基带频率的相位旋转的装置可以包括主发射信号路径和分集发射信号路径。 主发射信号路径和分集发射信号路径都可以接收主发射信号。 在主发射信号处于基带频率的同时，分集发射信号路径内的信号选择器可以执行相对于主发射信号的相位旋转，从而产生分集发射信号。

    Direct conversion receiver architecture
    6.
    发明申请
    Direct conversion receiver architecture 有权
    直接转换接收机架构

    公开(公告)号：US20050208916A1

    公开(公告)日：2005-09-22

    申请号：US11131147

    申请日：2005-05-16

    申请人： Paul Peterzell ,  Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    发明人： Paul Peterzell ,  Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Matthew Severson

    IPC分类号： H03G1/00 ,  H03G3/20 ,  H03G3/30 ,  H04L27/22 ,  H04L27/38 ,  H04B1/06 ,  H04B1/26 ,  H04B7/00

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。

    Systems and methods for producing a predetermined output in a sequential circuit during power on
    8.
    发明授权
    Systems and methods for producing a predetermined output in a sequential circuit during power on 有权
    在上电期间在顺序电路中产生预定输出的系统和方法

    公开(公告)号：US08446188B2

    公开(公告)日：2013-05-21

    申请号：US12762992

    申请日：2010-04-19

    申请人： Kashyap R. Bellur ,  Anosh B. Davierwalla ,  Christian Holenstein

    发明人： Kashyap R. Bellur ,  Anosh B. Davierwalla ,  Christian Holenstein

    IPC分类号： H03L7/00

    CPC分类号： H03K19/0013 ,  H03K17/22 ,  H03K19/018521

    摘要： An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.

    摘要翻译： 公开了一种被配置为在通电期间在顺序电路中产生预定输出的集成电路。 集成电路包括耦合到一个或多个内部节点的一个或多个电容器。 如果电源节点处的电压以一段时间或更快的速度上升到设定的电压，则一个或多个电容器对内部节点进行充电。 集成电路还包括耦合到电源节点的第一晶体管。 当电源节点上的电压上升到设定电压时，第一晶体管产生对一个或多个内部节点充电的泄漏电流，不会比时间段更快。 集成电路还包括输出节点。 输出节点上的逻辑值基于充电内部节点上的逻辑值，当时序电路的输入信号不起作用并且电源节点上的电压处于设定电压时。

    SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON
    9.
    发明申请
    SYSTEMS AND METHODS FOR PRODUCING A PREDETERMINED OUTPUT IN A SEQUENTIAL CIRCUIT DURING POWER ON 有权
    在通电期间在顺序电路中生成预测输出的系统和方法

    公开(公告)号：US20100289537A1

    公开(公告)日：2010-11-18

    申请号：US12762992

    申请日：2010-04-19

    申请人： Kashyap R. Bellur ,  Anosh B. Davierwalla ,  Christian Holenstein

    发明人： Kashyap R. Bellur ,  Anosh B. Davierwalla ,  Christian Holenstein

    IPC分类号： H03L7/00

    CPC分类号： H03K19/0013 ,  H03K17/22 ,  H03K19/018521

    摘要： An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.

    摘要翻译： 公开了一种被配置为在通电期间在顺序电路中产生预定输出的集成电路。 集成电路包括耦合到一个或多个内部节点的一个或多个电容器。 如果电源节点处的电压以一段时间或更快的速度上升到设定电压，则一个或多个电容器对内部节点进行充电。 集成电路还包括耦合到电源节点的第一晶体管。 当电源节点上的电压上升到设定电压时，第一晶体管产生对一个或多个内部节点充电的泄漏电流，不会比时间段更快。 集成电路还包括输出节点。 输出节点上的逻辑值基于充电内部节点上的逻辑值，当时序电路的输入信号不起作用并且电源节点上的电压处于设定电压时。

    Variable gain selection in direct conversion receiver
    10.
    发明授权
    Variable gain selection in direct conversion receiver 失效
    直接转换接收机中的可变增益选择

    公开(公告)号：US07076225B2

    公开(公告)日：2006-07-11

    申请号：US10034734

    申请日：2001-12-21

    申请人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    发明人： Tao Li ,  Christian Holenstein ,  Inyup Kang ,  Brett C. Walker ,  Paul E. Peterzell ,  Raghu Challa ,  Matthew L. Severson ,  Arun Raghupathy ,  Gilbert Christopher Sih

    IPC分类号： H04B7/00

    CPC分类号： H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

    摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

    摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。