公开(公告)号：US06714961B1

公开(公告)日：2004-03-30

申请号：US09438923

申请日：1999-11-12

申请人： Per Anders Holmberg ,  Terje Egeland ,  Nils Ola Linnermark ,  Karl Oscar Joachim Strömbergson ,  Magnus Carlsson

发明人： Per Anders Holmberg ,  Terje Egeland ,  Nils Ola Linnermark ,  Karl Oscar Joachim Strömbergson ,  Magnus Carlsson

IPC分类号： G06F900

CPC分类号： G06F9/5027 ,  G06F9/3842 ,  G06F9/3851

摘要： The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to the processing unit for speculative execution of a corresponding first job, and a further job signal is assigned to the processing unit for speculative execution of a corresponding further job. The speculative execution of said further job is initiated when the processing unit has completed execution of the first job. If desirable, even more job signals may be assigned to the processing unit for speculative execution. In this way, multiple job signals are assigned to the processing units of the processing system, and the processing units are allowed to execute a plurality of jobs speculatively while waiting for commit priority. By assigning multiple job signals for speculative execution by one or more processing units, the effects of variations in execution time between jobs are neutralized, and the overall performance of the processing system is substantially improved.

摘要翻译： 本发明涉及具有多个处理单元的多处理系统。 对于多处理系统中的至少一个处理单元，第一作业信号被分配给处理单元用于相应的第一作业的推测执行，并且另外的作业信号被分配给处理单元，用于推测执行相应的另一个 工作。 当处理单元已经完成第一作业的执行时，启动所述另外的作业的推测执行。 如果需要，则甚至可以将更多的作业信号分配给处理单元用于投机执行。 以这种方式，将多个作业信号分配给处理系统的处理单元，并且允许处理单元在等待提交优先级时推测地执行多个作业。 通过分配多个作业信号用于由一个或多个处理单元进行推测执行，中和了作业之间执行时间的变化的影响，并且处理系统的整体性能得到显着提高。

公开(公告)号：US07565658B2

公开(公告)日：2009-07-21

申请号：US10491880

申请日：2001-10-08

申请人： Tomas Ericsson ,  Per Anders Holmberg ,  Fredrik Strandberg ,  Lars Winberg ,  Nils Ola Linnermark

发明人： Tomas Ericsson ,  Per Anders Holmberg ,  Fredrik Strandberg ,  Lars Winberg ,  Nils Ola Linnermark

IPC分类号： G06F9/46 ,  G06F15/173

CPC分类号： G06F9/4843

摘要： The read latency caused by job start preparation of a future job is at least partly hidden within the current job by reading information for job start preparation of the future job integrated with the execution of the current job. Instructions for job start preparation are preferably instrumented (701) into the current job and executed (702), whenever possible, in parallel with the instructions of the current job. The integrated job start preparation may include table look-ups, register file updating, instruction fetching and preparation. If the scheduled job order is allowed to change during execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution of the next job and take appropriate actions (704; 705, 706) depending on the outcome of the test. In addition to reduced job start preparation time, unused slots in the instruction-parallel execution of the current job may be filled up by the added read instructions, thus providing more efficient utilization of the multiple functional execution units of the processor.

摘要翻译： 由作业开始准备未来作业引起的读延迟至少部分隐藏在当前作业中，通过阅读与当前作业的执行相集成的未来作业的作业开始准备的信息。 最好将作业开始准备的说明书（701）装入当前作业，并尽可能与当前作业的指令并行执行（702）。 集成作业开始准备可以包括表查找，寄存器文件更新，指令提取和准备。 如果在执行期间允许调度的作业命令改变，则在开始执行之前通常需要测试（703）下一个作业是否仍然有效，通常需要测试（703）下一个作业是否仍然有效 开始执行下一个工作，并根据测试的结果采取适当的措施（704; 705,706）。 除了减少作业开始准备时间之外，当前作业的指令并行执行中的未使用的插槽可以被添加的读取指令填充，从而提供对处理器的多个功能执行单元的更有效的利用。

公开(公告)号：US06865736B2

公开(公告)日：2005-03-08

申请号：US09784070

申请日：2001-02-16

申请人： Per Anders Holmberg ,  Peter Norrman ,  Leif Karl Johansson ,  Terje Egeland

发明人： Per Anders Holmberg ,  Peter Norrman ,  Leif Karl Johansson ,  Terje Egeland

IPC分类号： G06F11/34 ,  G06F12/08 ,  G06F9/49

CPC分类号： G06F9/5016 ,  G06F11/3409 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

摘要： The present invention discloses a processor system comprising a processor (31) and at least a first memory (32) and a second memory (34, 36, 37). The first memory (32) is normally faster than the second one, and means for memory allocation (38, 41, 48) perform the periodically static allocation of data into the first memory (32). The means for memory allocation (38, 41, 48) are run-time updateable by software. An execution profiling section (39) is provided for continuously or intermittently providing execution data used for updating the means for memory allocation (38, 41, 48). According to the invention, the memory allocation is performed on a variable or record (49, 50) level. The means for memory allocation preferably use linking tables (41, 48) supporting dynamic software changes. The first memory (32) is preferably an SRAM, connected to the processor by a dedicated bus (33).

摘要翻译： 本发明公开了一种包括处理器（31）和至少第一存储器（32）和第二存储器（34,36,37）的处理器系统。 第一存储器（32）通常比第二存储器（32）快，并且用于存储器分配（38,41,48）的装置执行数据到第一存储器（32）的周期性静态分配。 内存分配（38,41,48）的运行时间可由软件更新。 提供执行分析部分（39），用于连续地或间歇地提供用于更新用于存储器分配的装置（38,41,48）的执行数据。 根据本发明，对变量或记录（49,50）进行存储器分配。 用于存储器分配的装置优选地使用支持动态软件改变的链接表（41,48）。 第一存储器（32）优选地是通过专用总线（33）连接到处理器的SRAM。

公开(公告)号：US06662203B1

公开(公告)日：2003-12-09

申请号：US09438922

申请日：1999-11-12

申请人： Lars-Örjan Kling ,  Sten Edvard Johnson ,  Per Anders Holmberg ,  Terje Egeland

发明人： Lars-Örjan Kling ,  Sten Edvard Johnson ,  Per Anders Holmberg ,  Terje Egeland

IPC分类号： G06F900

CPC分类号： G06F9/4881

摘要： The present invention relates to multiprocessing systems in which signals or processes are scheduled in order of their priority level. The invention is based on batch-wise acceptance and scheduling of job signals, and utilizes at least one delay queue for temporarily storing job signals to the processing system before they are accepted for scheduling. The processing system further comprises circuitry for batch-wise insertion of the temporarily stored job signals into the job scheduler of the multiprocessing system. In this way, the utilization of the parallel processing units is increased and the number of changes between different priority levels in the multiprocessing system is minimized.

摘要翻译： 本发明涉及多处理系统，其中信号或过程按其优先级顺序排列。 本发明基于工作信号的分批接收和调度，并且在被接受进行调度之前利用至少一个延迟队列来临时存储作业信号给处理系统。 处理系统还包括用于将暂时存储的作业信号分批插入到多处理系统的作业调度器中的电路。 以这种方式，并行处理单元的利用率增加，多处理系统中的不同优先级之间的变化次数最小化。

公开(公告)号：US07725268B2

公开(公告)日：2010-05-25

申请号：US11791459

申请日：2004-11-25

申请人： Roger Marcel Appelo ,  Tom Urban Artursson ,  Per Anders Holmberg ,  Nicolae Barsan ,  Heiko Eugen Ulmer

发明人： Roger Marcel Appelo ,  Tom Urban Artursson ,  Per Anders Holmberg ,  Nicolae Barsan ,  Heiko Eugen Ulmer

IPC分类号： G06F19/00 ,  G06F7/00 ,  B60H1/00

CPC分类号： G01N33/0006

摘要： Method and sensing module for sensing pollution of outside air. The sensing module (1) comprises an electro chemical sensing element (3), and a processor (2). A sensing module output signal is provided based on the measurement signal and a baseline signal level. The baseline signal level is adapted depending on two threshold levels (13-15). A pollution concentration value is determined from the measurement signal and a classification level of air pollution is provided as sensing module output signal. A classification level is determined using a plurality of classification threshold values and the pollution concentration values. The plurality of classification threshold values are dynamically adjustable.

摘要翻译： 用于感应外部空气污染的方法和传感模块。 感测模块​​（1）包括电化学感测元件（3）和处理器（2）。 基于测量信号和基线信号电平提供感测模块输出信号。 基准信号电平根据两个阈值电平进行调整（13-15）。 从测量信号确定污染浓度值，并提供空气污染的分类等级作为感测模块输出信号。 使用多个分类阈值和污染浓度值来确定分类水平。 多个分类阈值是可动态调整的。

公开(公告)号：US07545646B2

公开(公告)日：2009-06-09

申请号：US11917669

申请日：2005-06-23

申请人： Per Anders Holmberg ,  Ulf Eric Andretzky

发明人： Per Anders Holmberg ,  Ulf Eric Andretzky

IPC分类号： H05K7/20 ,  H01L23/36

CPC分类号： H05K1/0272 ,  F28D15/0275 ,  F28F1/12 ,  F28F1/20 ,  H01L23/427 ,  H01L2924/0002 ,  H05K2201/064 ,  H05K2201/066 ,  Y10T29/4935 ,  H01L2924/00

摘要： A cooling assembly and method of cooling a heat-generating electronic component on a circuit board. A heat collector collects heat from the electronic component. A heat pipe transfers the heat to a location remote from the electronic component. A heat sink is mounted to the circuit board at the distant location. The heat sink has at least one groove formed on an underside thereof. The heat sink is mounted so that is overlies the heat pipe and the heat pipe is introduced into the groove, thereby securing the heat pipe between the heat sink and the circuit board.

摘要翻译： 一种用于冷却电路板上的发热电子部件的冷却组件和方法。 集热器从电子部件收集热量。 热管将热量传递到远离电子部件的位置。 散热器安装在距离较远位置的电路​​板上。 散热器具有形成在其下侧上的至少一个凹槽。 散热器安装成使其覆盖在热管上，并且热管被引入槽中，从而将热管固定在散热器和电路板之间。

公开(公告)号：US06665708B1

公开(公告)日：2003-12-16

申请号：US09438320

申请日：1999-11-12

申请人： Nikhil Tikekar ,  Per Anders Holmberg

发明人： Nikhil Tikekar ,  Per Anders Holmberg

IPC分类号： G06F1516

CPC分类号： G06F9/52

摘要： A computer system performs a coarse-grained dependency checking between concurrently executed jobs that share a memory. First and second jobs are defined, each having a set of shared individually addressable data items stored in a corresponding set of locations within a memory. The set of locations are partitioned into a set of data areas, wherein at least one of the data areas stores more than one of the data items. The first and second jobs are then run. To determine whether a collision has occurred between the first job and the second job, it is determined whether the first job accessed a same data area as was accessed by the second job, regardless of whether a same data item within the same data area was accessed by both the first job and the second job.

摘要翻译： 计算机系统在共享内存的并发执行作业之间执行粗粒度依赖关系检查。 定义第一和第二作业，每个具有存储在存储器内的相应的一组位置中的一组共享的单独可寻址的数据项。 该组位置被划分成一组数据区域，其中数据区域中的至少一个存储多于一个的数据项。 然后运行第一个和第二个作业。 为了确定在第一作业和第二作业之间是否发生冲突，确定第一作业是否访问与第二作业所访问的相同的数据区域，而不管相同数据区域内的相同数据项是否被访问 通过第一份工作和第二份工作。

公开(公告)号：US06539458B2

公开(公告)日：2003-03-25

申请号：US09840468

申请日：2001-04-24

申请人： Per Anders Holmberg

发明人： Per Anders Holmberg

IPC分类号： G06F1208

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3804 ,  G06F12/0862 ,  G06F2212/6028

摘要： A data processing system and method involving a data requesting element and a first memory element from which said data requesting element requests data is described. An example of such a system is a processor and a first level cache memory, or two memories arranged in a hierarchy. A second memory element is provided between the first memory element and the requesting element. The second memory element stores data units read out of said first memory element, and performs a prefetch procedure, where said prefetch procedure contains both a sequential sub-procedure and a sub-procedure based on prefetch data identifiers associated with some of the data units.

摘要翻译： 描述了涉及数据请求元素和所述数据请求元件从其请求数据的第一存储器元件的数据处理系统和方法。 这种系统的一个例子是处理器和一级高速缓冲存储器，或两个以层次结构排列的存储器。 在第一存储器元件和请求元件之间提供第二存储元件。 第二存储器元件存储从所述第一存储器元件读出的数据单元，并且执行预取过程，其中所述预取过程基于与一些数据单元相关联的预取数据标识符，包含顺序子过程和子过程两者。

公开(公告)号：US06247141B1

公开(公告)日：2001-06-12

申请号：US09159771

申请日：1998-09-24

申请人： Per Anders Holmberg

发明人： Per Anders Holmberg

IPC分类号： G06F1114

CPC分类号： G06F11/1451 ,  Y10S707/99931

摘要： A fault-tolerant client-server system has a primary server, a backup server; and a client. The client sends a request to the primary server, which receives and processes the request, including sending the response to the client, independent of any backup processing. The response includes the primary server state information. The primary server also performs backup processing that includes periodically sending the primary server state information to the backup server. The client receives the response from the primary server, and sends the primary server state information to the backup server. The primary server state information includes all request-reply pairs that the primary server has handled since a most recent transmission of primary server state information from the primary server to the backup server. The primary server's backup processing may be activated periodically based on a predetermined time interval. Alternatively, it may be activated when the primary server's memory for storing the primary server state information is filled to a predetermined amount.

摘要翻译： 容错客户端 - 服务器系统具有主服务器，备份服务器; 和客户端。 客户端向主服务器发送请求，该主服务器接收并处理请求，包括将响应发送到客户端，而与任何备份处理无关。 响应包括主服务器状态信息。 主服务器还执行备份处理，包括定期向备份服务器发送主服务器状态信息。 客户端从主服务器接收响应，并将主服务器状态信息发送到备份服务器。 主服务器状态信息包括主服务器自主服务器状态信息从主服务器到备份服务器的最新传输之后所处理的所有请求 - 回复对。 可以基于预定的时间间隔周期性地激活主服务器的备份处理。 或者，当用于存储主服务器状态信息的主服务器的存储器被填充到预定量时，可以激活它。

公开(公告)号：US06457145B1

公开(公告)日：2002-09-24

申请号：US09354988

申请日：1999-07-16

申请人： Per Anders Holmberg ,  Dan Olov Halvarsson ,  Tomas Jonsson

发明人： Per Anders Holmberg ,  Dan Olov Halvarsson ,  Tomas Jonsson

IPC分类号： H02H305

CPC分类号： G06F11/27

摘要： For fault testing in a digital system, a processor unit is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyze is activated and the processor unit generates a set of stimuli, influencing the appropriate logical units. The output response analyzer collects responses to the stimuli at different nodes in the digital system and creates signatures from them. The signals are verified and if a fault is noticed, this error is noticed. The present state of the processor and other logical units are stored in a storage device prior to the test and recovered after the testing is finished. This fault testing can be performed both at chip and board levels, and on systems with several units.

摘要翻译： 对于数字系统中的故障测试，可以从其他活动获得处理器单元，并且将要测试的逻辑单元设置为预定状态。 输出响应分析被激活，并且处理器单元产生一组刺激，影响适当的逻辑单元。 输出响应分析器收集对数字系统中不同节点处的刺激的响应，并从中创建签名。 信号被验证，如果发现故障，则会发现该错误。 处理器和其他逻辑单元的当前状态在测试之前存储在存储设备中，并且在测试完成之后被恢复。 这种故障测试可以在芯片和电路板级以及具有多个单元的系统上进行。