公开(公告)号：US07631307B2

公开(公告)日：2009-12-08

申请号：US10728649

申请日：2003-12-05

申请人： Perry H. Wang ,  Hong Wang ,  John P. Shen ,  Ashok N. Seshadri ,  Anthony N. Mah ,  William R. Greene ,  Ravi K. Chandran ,  Piyush Desai ,  Steve Shih-wei Liao

发明人： Perry H. Wang ,  Hong Wang ,  John P. Shen ,  Ashok N. Seshadri ,  Anthony N. Mah ,  William R. Greene ,  Ravi K. Chandran ,  Piyush Desai ,  Steve Shih-wei Liao

IPC分类号： G06F9/46 ,  G06F3/00 ,  G06F15/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/542

摘要： A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

摘要翻译： 虚拟多线程硬件机制在单线程处理器上提供多线程。 线程切换由用户定义的触发器触发。 可以以特殊触发指令的形式定义同步触发。 可以通过标识异步触发条件的特殊标记指令定义异步触发。 异步触发条件可以基于多个原子处理器事件。 在线程切换时，由硬件维护的最小上下文信息，例如仅指令指针地址。 与传统的同时多线程方案相反，虚拟多线程硬件提供对操作系统透明的线程切换，可以在不进行操作系统干预的情况下执行。

公开(公告)号：US08868887B2

公开(公告)日：2014-10-21

申请号：US10982261

申请日：2004-11-05

申请人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

发明人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

IPC分类号： G06F9/00

CPC分类号： G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US20050125802A1

公开(公告)日：2005-06-09

申请号：US10728649

申请日：2003-12-05

申请人： Perry Wang ,  Hong Wang ,  John Shen ,  Ashok Seshadri ,  Anthony Mah ,  William Greene ,  Ravi Chandran ,  Piyush Desai ,  Steve Liao

发明人： Perry Wang ,  Hong Wang ,  John Shen ,  Ashok Seshadri ,  Anthony Mah ,  William Greene ,  Ravi Chandran ,  Piyush Desai ,  Steve Liao

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/542

摘要： A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may be based on a plurality of atomic processor events. Minimal context information, such as only an instruction pointer address, is maintained by the hardware upon a thread switch. In contrast to traditional simultaneous multithreading schemes, the virtual multithreading hardware provides thread switches that are transparent to an operating system and that may be performed without operating system intervention.

摘要翻译： 虚拟多线程硬件机制在单线程处理器上提供多线程。 线程切换由用户定义的触发器触发。 可以以特殊触发指令的形式定义同步触发。 可以通过标识异步触发条件的特殊标记指令定义异步触发。 异步触发条件可以基于多个原子处理器事件。 在线程切换时，由硬件维护的最小上下文信息，例如仅指令指针地址。 与传统的同时多线程方案相反，虚拟多线程硬件提供对操作系统透明的线程切换，可以在不进行操作系统干预的情况下执行。

公开(公告)号：US07487502B2

公开(公告)日：2009-02-03

申请号：US10370251

申请日：2003-02-19

申请人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

发明人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F9/45

CPC分类号： G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US20050166039A1

公开(公告)日：2005-07-28

申请号：US10982261

申请日：2004-11-05

申请人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

发明人： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F11/34

CPC分类号： G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US20060294427A1

公开(公告)日：2006-12-28

申请号：US11167965

申请日：2005-06-27

申请人： Richard Glass ,  Madhu Athreya ,  Keith Drescher ,  Piyush Desai

发明人： Richard Glass ,  Madhu Athreya ,  Keith Drescher ,  Piyush Desai

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

公开(公告)号：US20060107120A1

公开(公告)日：2006-05-18

申请号：US11300423

申请日：2005-12-15

申请人： Ayman Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn Merrell

发明人： Ayman Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn Merrell

IPC分类号： G06F11/00

CPC分类号： G06F11/24 ,  G06F11/27

摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

公开(公告)号：US07496801B2

公开(公告)日：2009-02-24

申请号：US11167965

申请日：2005-06-27

申请人： Richard J. Glass ,  Madhu S. Athreya ,  Keith A. Drescher ,  Piyush Desai

发明人： Richard J. Glass ,  Madhu S. Athreya ,  Keith A. Drescher ,  Piyush Desai

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A scheme for exposing internal debug values in an in-band means via debug packets that are injected sequentially with normal link traffic on a link and do not interrupt or otherwise interfere with normal operation of the link or related devices. Therefore, this proposal does not require additional pins since the debug values are exposed via debug packets in an in-band means along with normal link traffic and the debug values are exposed synchronously with normal link traffic since the debug packets are injected sequentially.

摘要翻译： 通过与链路上的正常链路业务顺序注入的调试分组来暴露带内装置中的内部调试值的方案，并且不会中断或以其他方式干扰链路或相关设备的正常操作。 因此，该提案不需要额外的引脚，因为调试值通过带内装置中的调试分组以及正常链路业务暴露，并且调试值与正常链路业务同步地暴露，因为调试分组被顺序注入。

公开(公告)号：US07487398B2

公开(公告)日：2009-02-03

申请号：US11300423

申请日：2005-12-15

申请人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

发明人： Ayman G. Abdo ,  Cameron McNairy ,  Piyush Desai ,  Quinn W. Merrell

IPC分类号： G06F11/00

CPC分类号： G06F11/24 ,  G06F11/27

摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

摘要翻译： 通过在总线上产生骚扰事务来测试计算机系统的元素。 在总线上检测到第一个事务。 第一个事务包括对第一个地址的第一个数据请求。 响应并且基于检测到第一地址，生成第二数据请求到第二地址。 第二个数据请求作为第二个事务在总线上发出，而总线上第一个事务处于待处理状态。

公开(公告)号：US20060238158A1

公开(公告)日：2006-10-26

申请号：US11114652

申请日：2005-04-26

申请人： Ali Emadi ,  Fernando Rodriguez ,  Piyush Desai

发明人： Ali Emadi ,  Fernando Rodriguez ,  Piyush Desai

IPC分类号： H02P5/00

CPC分类号： H02P27/10 ,  H02P6/34 ,  H02P2209/07

摘要： A digital controller is easily implemented for variable speed or torque control of an electric motor or generator by using a comparator to determine a choice of control state outputs.

摘要翻译： 通过使用比较器来确定控制状态输出的选择，可以容易地实现用于电动机或发电机的可变速度或转矩控制的数字控制器。