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    Dual Cavity Etch for Embedded Stressor Regions
    1.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。

    Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures
    2.
    发明申请
    Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures 有权
    形成对栅极电极结构提供增强保护的间隔物的方法

    公开(公告)号：US20120292671A1

    公开(公告)日：2012-11-22

    申请号：US13108363

    申请日：2011-05-16

    申请人： Peter Baars ,  Sven Beyer ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Peter Baars ,  Sven Beyer ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L21/3213 ,  H01L29/78

    CPC分类号： H01L29/66772 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/78618 ,  H01L29/78687

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区，其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区， 位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物，和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

    INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH
    6.
    发明申请
    INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH 审中-公开
    通过在应力衬里方法中实施附加清洁过程来提高晶体管性能

    公开(公告)号：US20130295767A1

    公开(公告)日：2013-11-07

    申请号：US13462246

    申请日：2012-05-02

    申请人： Thilo Scheiper ,  Peter Baars

    发明人： Thilo Scheiper ,  Peter Baars

    IPC分类号： H01L21/28 ,  H01L21/3065

    CPC分类号： H01L21/823807 ,  H01L21/0206 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

    摘要： When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.

    摘要翻译： 当基于形成在晶体管上方的高应力电介质材料形成复杂的晶体管时，通过在沉积高应力材料之前减小栅电极结构的间隔结构的尺寸，可以增加应力传递效率。 在沉积高应力材料之前，可以实施额外的清洁工艺，以减少任何金属污染物的存在，特别是在栅电极结构附近，否则会导致增加的边缘电容。

    Superior integrity of high-k metal gate stacks by forming STI regions after gate metals
    7.
    发明授权
    Superior integrity of high-k metal gate stacks by forming STI regions after gate metals 有权
    通过在栅极金属之后形成STI区域，高k金属栅极叠层具有优异的完整性

    公开(公告)号：US08609509B2

    公开(公告)日：2013-12-17

    申请号：US13239943

    申请日：2011-09-22

    申请人： Thilo Scheiper ,  Peter Baars

    发明人： Thilo Scheiper ,  Peter Baars

    IPC分类号： H01L21/76 ,  H01L21/70

    CPC分类号： H01L21/76232 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878

    摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.

    摘要翻译： 当在早期制造阶段形成复杂的高k金属栅极电极结构时，可以通过在形成隔离物之前形成和图案化敏感栅极材料来实现优异的工艺鲁棒性，降低的屈服损失和提高设计整个工艺流程的灵活性 地区。

    Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask
    9.
    发明授权
    Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask 有权
    晶体管具有基于硬掩模的早期处理阶段形成的沟道半导体合金

    公开(公告)号：US08377773B1

    公开(公告)日：2013-02-19

    申请号：US13285600

    申请日：2011-10-31

    申请人： Thilo Scheiper ,  Peter Baars

    发明人： Thilo Scheiper ,  Peter Baars

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823878

    摘要： Generally, the present disclosure is directed to methods for adjusting transistor characteristics by forming a semiconductor alloy in the channel region of the transistor during early device processing. One disclosed method includes forming an isolation structure in a semiconductor layer of a semiconductor device and in a threshold voltage adjusting semiconductor alloy formed on the semiconductor layer, the isolation structure laterally separating a first active region and a second active region. The method also includes introducing a first and second well dopant species through the threshold voltage adjusting semiconductor alloy and into the first and second active regions, respectively, then removing the threshold voltage adjusting semiconductor alloy selectively from the second active region, and forming a first gate electrode structure of a first transistor on the threshold voltage adjusting semiconductor alloy of the first active region a second gate electrode structure of a second transistor on the second active region.

    摘要翻译： 通常，本公开涉及通过在早期器件处理期间在晶体管的沟道区域中形成半导体合金来调整晶体管特性的方法。 一种公开的方法包括在半导体器件的半导体层中形成隔离结构，以及在半导体层上形成的阈值电压调节半导体合金中，隔离结构横向分离第一有源区和第二有源区。 该方法还包括分别通过阈值电压调节半导体合金引入第一和第二阱掺杂剂物质并分别进入第一和第二有源区，然后从第二有源区选择性地去除阈值电压调整半导体合金，以及形成第一栅极 在第一有源区的阈值电压调节半导体合金上的第一晶体管的电极结构，第二有源区上的第二晶体管的第二栅电极结构。

    Method of Forming Contacts for Devices with Multiple Stress Liners
    10.
    发明申请
    Method of Forming Contacts for Devices with Multiple Stress Liners 有权
    形成具有多个应力衬垫的装置的触点的方法

    公开(公告)号：US20120299160A1

    公开(公告)日：2012-11-29

    申请号：US13116672

    申请日：2011-05-26

    申请人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

    发明人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

    IPC分类号： H01L21/311 ,  H01L23/58

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层 所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。 该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层 至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。 在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。