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111 条记录 (耗时 0.032 秒)

    Integrated tray converter
    4.
    发明授权
    Integrated tray converter 有权
    集成托盘转换器

    公开(公告)号：US08142133B2

    公开(公告)日：2012-03-27

    申请号：US12394599

    申请日：2009-02-27

    申请人： Mark Neebe ,  Matthew Good ,  Charles Miller

    发明人： Mark Neebe ,  Matthew Good ,  Charles Miller

    IPC分类号： B65G59/00 ,  B65G59/06

    CPC分类号： B07C3/00

    摘要： A method and system for converting mail between trays in a multiple pass mail sorting system using a plurality of different tray types. Mail from a first type of tray is unloaded and stacked along with mail from other trays to form a large stack. The large stack of mail is then broken down into smaller stacks which are transferred to one of several outputs where the mail is loaded into different types of trays.

    摘要翻译： 一种用于在多遍邮件分拣系统中的托盘之间转换邮件的方法和系统，其使用多种不同的托盘类型。 来自第一种类型的托盘的邮件与其他托盘的邮件一起卸载和堆叠以形成大堆栈。 然后将大堆邮件分解成更小的堆栈，这些堆栈被传送到几个输出中的一个，邮件被加载到不同类型的托盘中。

    Method and apparatus for terminating a test signal applied to multiple semiconductor loads under test
    5.
    发明授权
    Method and apparatus for terminating a test signal applied to multiple semiconductor loads under test 有权
    用于终止应用于被测试的多个半导体负载的测试信号的方法和装置

    公开(公告)号：US08098076B2

    公开(公告)日：2012-01-17

    申请号：US12416375

    申请日：2009-04-01

    申请人： Guang Chen ,  Charles Miller ,  David Pritzkau

    发明人： Guang Chen ,  Charles Miller ,  David Pritzkau

    IPC分类号： G01R31/20

    CPC分类号： G01R31/31905

    摘要： Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential.

    摘要翻译： 描述了用于终止施加到被测试的多个半导体负载的测试信号的装置，例如用于在测试器和待测半导体器件（DUT）之间接合测试信号的装置。 在一些示例中，探针卡组件可以包括至少一个探针基板，每个探针基板具有被配置为接触DUT的测试特征的测试探针; 耦合到所述至少一个探针衬底的布线衬底，具有被配置为与测试器的源端接耦合的连接器; 形成在布线基板和至少一个探针基板上和/或布线基板和至少一个探针基板上的信号路径，该信号路径具有从迹线扇出的迹线和迹线短线，迹线的输入耦合到连接器和迹线的输出 桩被耦合到测试探针; 以及耦合在迹线和至少一个电位之间的电阻终端。

    Method And System For Treating A Subterranean Formation Using Diversion
    6.
    发明申请
    Method And System For Treating A Subterranean Formation Using Diversion 有权
    使用引水处理地下地层的方法和系统

    公开(公告)号：US20110186298A1

    公开(公告)日：2011-08-04

    申请号：US13045146

    申请日：2011-03-10

    申请人： W. E. Clark ,  Doug Bentley ,  John Daniels ,  Christopher N. Fredd ,  Charles Miller ,  John Lassek

    发明人： W. E. Clark ,  Doug Bentley ,  John Daniels ,  Christopher N. Fredd ,  Charles Miller ,  John Lassek

    IPC分类号： E21B43/00 ,  E21B19/00 ,  E21B21/00

    CPC分类号： E21B43/12 ,  E21B43/14 ,  E21B43/25

    摘要： A method well treatment includes establishing fluid connectivity between a wellbore and at least one target zone for treatment within a subterranean formation, which is intersected by a wellbore. The method includes deploying coiled tubing into the wellbore and introducing a treatment composition into the wellbore. The method includes contacting a target zone within the subterranean formation with the treatment composition, introducing a diversion agent through the coiled tubing to an interval within a wellbore and repeating the introduction of the treatment, the contacting of the target zone and the introduction of the diversion agent for more than one target zone.

    摘要翻译： 一种方法井处理包括在井​​眼与至少一个目标区域之间建立流体连通性，以在地下地层内进行处理，该地层与井眼相交。 该方法包括将连续油管部署到井眼中并将处理组合物引入井眼。 该方法包括将地下地层内的目标区域与处理组合物接触，将引导剂通过连续油管引入井筒内的间隔，并重复进行处理，目标区域的接触和引入引导 代理多个目标区域。

    Method and system for treating a subterranean formation using diversion
    7.
    发明授权
    Method and system for treating a subterranean formation using diversion 有权
    使用转移处理地下地层的方法和系统

    公开(公告)号：US07934556B2

    公开(公告)日：2011-05-03

    申请号：US11751172

    申请日：2007-05-21

    申请人： William Ernest Clark ,  Doug Bentley ,  John Daniels ,  Christopher N. Fredd ,  Charles Miller ,  John Lassek

    发明人： William Ernest Clark ,  Doug Bentley ,  John Daniels ,  Christopher N. Fredd ,  Charles Miller ,  John Lassek

    IPC分类号： E21B43/14 ,  E21B47/10

    CPC分类号： E21B43/12 ,  E21B43/14 ,  E21B43/25

    摘要： A method well treatment includes establishing fluid connectivity between a wellbore and at least one target zone for treatment within a subterranean formation, which is intersected by a wellbore. The method includes deploying coiled tubing into the wellbore and introducing a treatment composition into the wellbore. The method includes contacting a target zone within the subterranean formation with the treatment composition, introducing a diversion agent through the coiled tubing to an interval within a wellbore and repeating the introduction of the treatment, the contacting of the target zone and the introduction of the diversion agent for more than one target zone.

    摘要翻译： 一种方法井处理包括在井​​眼与至少一个目标区域之间建立流体连通性，以在地下地层内进行处理，该地层与井眼相交。 该方法包括将连续油管部署到井眼中并将处理组合物引入井眼。 该方法包括将地下地层内的目标区域与处理组合物接触，将引导剂通过连续油管引入井筒内的间隔，并重复进行处理，目标区域的接触和引入引导 代理多个目标区域。

    INTEGRATED TRAY CONVERTER
    9.
    发明申请
    INTEGRATED TRAY CONVERTER 有权
    集成托盘转换器

    公开(公告)号：US20090317224A1

    公开(公告)日：2009-12-24

    申请号：US12394599

    申请日：2009-02-27

    申请人： Mark Neebe ,  Matthew Good ,  Charles Miller

    发明人： Mark Neebe ,  Matthew Good ,  Charles Miller

    IPC分类号： B65H83/00 ,  B65G57/00 ,  B07C1/00 ,  B07C99/00

    CPC分类号： B07C3/00

    摘要： A method and system for converting mail between trays in a multiple pass mail sorting system using a plurality of different tray types. Mail from a first type of tray is unloaded and stacked along with mail from other trays to form a large stack. The large stack of mail is then broken down into smaller stacks which are transferred to one of several outputs where the mail is loaded into different types of trays.

    摘要翻译： 一种用于在多遍邮件分拣系统中的托盘之间转换邮件的方法和系统，其使用多种不同的托盘类型。 来自第一种类型的托盘的邮件与其他托盘的邮件一起卸载和堆叠以形成大堆栈。 然后将大堆邮件分解成更小的堆栈，这些堆栈被传送到几个输出中的一个，邮件被加载到不同类型的托盘中。

    Intelligent probe card architecture
    10.
    发明申请
    Intelligent probe card architecture 审中-公开
    智能探针卡架构

    公开(公告)号：US20080100320A1

    公开(公告)日：2008-05-01

    申请号：US12001281

    申请日：2007-12-11

    申请人： Charles Miller ,  Matthew Chraft ,  Roy Henson

    发明人： Charles Miller ,  Matthew Chraft ,  Roy Henson

    IPC分类号： G01R31/26

    CPC分类号： G01R31/31905 ,  G01R1/07385 ,  G01R1/36 ,  G01R31/2889 ,  G01R35/00

    摘要： A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

    摘要翻译： 用于晶片测试系统的探针卡具有多个板上特征，使扇出测试系统控制器通道以测试晶片上的多个DUT，同时限制扇出对测试结果的不期望的影响。 探头卡的板载功能包括以下一个或多个功能：（a）通过将电阻器与每个DUT输入串联放置来隔离故障DUT提供的DUT信号隔离; （b）与每个DUT电源引脚串联的开关，限流器或稳压器提供的DUT电源隔离，以将电源与失效的DUT隔离; （c）使用板载微控制器或FPGA提供的自检; （d）作为探针卡的一部分提供的堆叠子卡，以适应额外的板上测试电路; 和（e）在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或基板和测试系统控制器之间的接口线的数量 。