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公开(公告)号：US06858883B2
公开(公告)日：2005-02-22
申请号：US10454552
申请日：2003-06-03
CPC分类号： H01L27/2418 , H01L27/101 , H01L27/224 , H01L27/2481
摘要： A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.
摘要翻译： 一种包括第一电极，存储器存储元件和控制元件的存储器系统。 控制元件具有击穿电压。 通过部分处理控制元件来增加击穿电压。 在一个方面，通过处理比存储器存储元件更短的持续时间的控制元件来实现部分处理。 在另一方面，通过从多个层形成控制元件的部分处理结果，多个层中的一些层是未处理的，而多个层中的其他层被完全处理。
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公开(公告)号：US06625055B1
公开(公告)日：2003-09-23
申请号：US10120113
申请日：2002-04-09
申请人： Kenneth K. Smith , Sarah M. Brandenberger , Darrel R. Bloomquist , Kenneth J. Eldredge , Andrew L. Van Brocklin , Peter J. Fricke
发明人： Kenneth K. Smith , Sarah M. Brandenberger , Darrel R. Bloomquist , Kenneth J. Eldredge , Andrew L. Van Brocklin , Peter J. Fricke
IPC分类号： G11C1100
CPC分类号： G11C11/5692
摘要： A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or based on the geometric shape of the memory component, where different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits.
摘要翻译： 描述了只读存储器件，其具有包括连接在导电迹线之间的存储器部件的非易失性存储器单元。 存储器部件形成为包括当电位被施加到所选择的存储器单元时指示电阻值的电阻器。 单个存储单元中的存储器组件的电阻值对应于多个逻辑位。 对应于一组逻辑位的存储器组件的电阻值可以基于形成存储器组件的电阻材料的厚度和/或面积，和/或基于存储器组件的几何形状，其中不同 电阻材料的几何形状具有不同的电阻值，其对应于不同的逻辑位组。
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公开(公告)号：US07816722B2
公开(公告)日：2010-10-19
申请号：US10772945
申请日：2004-02-04
IPC分类号： H01L29/76
CPC分类号： H01L27/101
摘要： A memory array has a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and has a memory cell disposed at each cross-point, each memory cell having a storage element and a control element coupled in series between a row conductor and a column conductor, and each control element including a silicon-rich insulator. Methods for fabricating the memory array are disclosed.
摘要翻译： 存储器阵列具有多个行导体和多个列导体，行导体和列导体布置成在交叉点处交叉，并且具有设置在每个交叉点处的存储单元，每个存储单元具有存储元件 以及串联耦合在行导体和列导体之间的控制元件，并且每个控制元件包括富硅绝缘体。 公开了制造存储器阵列的方法。
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公开(公告)号：US06501697B1
公开(公告)日：2002-12-31
申请号：US09976304
申请日：2001-10-11
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/06 , G11C11/16 , G11C11/56 , G11C11/5607 , G11C2207/063
摘要： A sense amplifier is provided for reading data in a multiple-state memory cell of a resistive memory array in response to a read voltage applied across the sensed memory cell, including a differential amplifier having first and second input nodes. A sense circuit determines the current in the memory cell with the read voltage applied thereto and applies a sense current representative of the memory cell current to the first input node of the differential amplifier. A reference circuit has first and second resistive elements for applying a reference current to the second input node of the differential amplifier to provide a reference value against which to compare the sense current to determine the state of the memory cell. The first resistive element has a resistance representative of a first state of the memory cell, and the second resistive element has a resistance representative of a second state of the memory cell. A voltage source for applying the read voltage across the first and second resistive elements to generate a reference current by averaging the currents through the first and second resistive elements. A first translator transistor applies the sense current to the first node of the differential amplifier. A second translator transistor applies the reference current to the second node of the differential amplifier. A comparator circuit is used to compare the signals at the first and second input nodes of the differential amplifier to provide an output indicative of the state of the sensed memory cell.
摘要翻译： 提供读出放大器，用于响应于在感测到的存储单元上施加的读取电压来读取电阻存储器阵列的多状态存储单元中的数据，包括具有第一和第二输入节点的差分放大器。 感测电路以施加读取电压的方式确定存储单元中的电流，并将表示存储单元电流的感测电流施加到差分放大器的第一输入节点。 参考电路具有第一和第二电阻元件，用于将参考电流施加到差分放大器的第二输入节点，以提供参考值，用于比较感测电流以确定存储器单元的状态。 第一电阻元件具有表示存储单元的第一状态的电阻，并且第二电阻元件具有表示存储单元的第二状态的电阻。 电压源，用于通过对通过第一和第二电阻元件的电流进行平均来施加跨越第一和第二电阻元件的读取电压以产生参考电流。 第一转换晶体管将感测电流施加到差分放大器的第一节点。 第二转换晶体管将参考电流施加到差分放大器的第二节点。 比较器电路用于比较差分放大器的第一和第二输入节点处的信号，以提供指示感测的存储器单元的状态的输出。
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公开(公告)号：US06818549B2
公开(公告)日：2004-11-16
申请号：US10382673
申请日：2003-03-05
IPC分类号： H01L218239
CPC分类号： H01L27/224
摘要： A magnetic memory cell made on a substrate has a first metal conductor, a first magnetic layer disposed on the first metal conductor, a planar interlayer dielectric (ILD) having a via opening extending through it to the first magnetic layer, a buried tunnel junction over the first magnetic layer within the via opening, a second magnetic layer filling the via opening and burying the tunnel junction, and a second metal conductor coupled to the second magnetic layer. Methods for using the memory cell in memories and other devices and methods specially adapted for fabrication of the memory cell are disclosed.
摘要翻译： 在基板上形成的磁存储单元具有第一金属导体，设置在第一金属导体上的第一磁性层，具有延伸穿过第一磁性层的通路孔的平面层间电介质（ILD），覆盖 通孔开口内的第一磁性层，填充通孔开口并埋入隧道结的第二磁性层以及耦合到第二磁性层的第二金属导体。 公开了在存储器中使用存储单元的方法以及专门用于制造存储单元的其它器件和方法。
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公开(公告)号：US08232960B2
公开(公告)日：2012-07-31
申请号：US12251076
申请日：2008-10-14
申请人： Peter J. Fricke , Alan R. Arthur
发明人： Peter J. Fricke , Alan R. Arthur
IPC分类号： G09G3/34
CPC分类号： G09G3/3446 , G09G2320/0242
摘要： Among various embodiments of the present disclosure, displaying electrophoretic particles can be performed by configuring an electrophoretic display for directed spreading of electrophoretic particles across a number of substantially planar display electrodes. Such a configuration can be accomplished by controlling planar spreading of the electrophoretic particles in an electrophoretic pixel with an electrical field between an in-plane storage electrode and an in-plane activation electrode. The in-plane activation electrode can be connected to an in-plane display electrode, which extends across a first area in the electrophoretic pixel adjacent to a display aperture having a second area that is substantially coextensive with the first area.
摘要翻译： 在本公开的各种实施方案中，显示电泳颗粒可以通过配置电泳显示器来执行，所述电泳显示器用于在多个基本上平面的显示电极上定向扩散电泳粒子。 这样的配置可以通过在面内存储电极和面内激活电极之间的电场中控制电泳像素中的电泳粒子的平面扩展来实现。 平面内激活电极可以连接到平面显示电极，该平面显示电极延伸穿过邻近显示孔的电泳像素中的第一区域，该显示孔具有与第一区域基本共同延伸的第二区域。
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公开(公告)号：US07724431B2
公开(公告)日：2010-05-25
申请号：US11540792
申请日：2006-09-29
摘要： A method and apparatus apply an electric field across active layer, wherein active layer is configured to change from a first light attenuating state to a second lesser light attenuating state in response to the applied the electric field and wherein the second lesser light attenuating state permits light to be reflected from a light reflective face.
摘要翻译： 一种方法和装置在有源层上施加电场，其中有源层被配置为响应于施加的电场而从第一光衰减状态改变到第二较小的光衰减状态，并且其中第二较小的光衰减状态允许光 从光反射面反射出来。
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公开(公告)号：US20090027303A1
公开(公告)日：2009-01-29
申请号：US11782755
申请日：2007-07-25
CPC分类号： G09G3/20 , G09G3/3644 , G09G2310/0221 , G09G2310/0267
摘要： Embodiments 1of an apparatus with first and second display panels and a resistor multiplexer are disclosed.
摘要翻译： 公开了具有第一和第二显示面板和电阻多路复用器的设备的实施例1。
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公开(公告)号：US09033469B2
公开(公告)日：2015-05-19
申请号：US14345658
申请日：2011-10-14
CPC分类号： B41J2/0455 , B41J2/04541 , B41J2/04548 , B41J2/0458 , B41J2/04581
摘要： A method and apparatus supply electrical current to a firing actuator of a printhead die across a high side switching transistor in a source follower arrangement and supply a regulated voltage, that is no greater than a concurrent voltage at a drain of the HSS transistor, to a gate of the high side switching transistor.
摘要翻译： 一种方法和装置向源极跟随器装置中的高侧开关晶体管提供电流至打印头芯片的点火致动器，并将不超过HSS晶体管漏极的并联电压的调节电压提供给 高侧开关晶体管的栅极。
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公开(公告)号：US06741384B1
公开(公告)日：2004-05-25
申请号：US10429144
申请日：2003-04-30
IPC分类号： G02B2600
CPC分类号： G09G3/3433 , G09G3/2011 , G09G2300/08 , G09G2310/027
摘要： An array of MEMS devices having column lines and row lines, such as a light modulator array, is controlled in response to an input signal by providing a number of discrete voltages, multiplexing from the discrete voltages a selected voltage to be applied to each MEMS device of the array, and enabling application of the selected discrete voltage to each MEMS device of the array.
摘要翻译： 通过提供多个离散电压来响应于输入信号来控制具有列线和行线（例如光调制器阵列）的MEMS器件阵列，从分立电压复用要施加到每个MEMS器件的选定电压 并且使得能够将所选择的分立电压应用于阵列的每个MEMS器件。
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