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1.发明授权Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权用于处理由处理电路执行的指令的数据处理装置和方法公开(公告)号：US07747839B2
公开(公告)日：2010-06-29
申请号：US12010305
申请日：2008-01-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30145 , G06F9/30149 , G06F9/30189 , G06F9/3816 , G06F9/382 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。
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公开(公告)号：US08347067B2
公开(公告)日：2013-01-01
申请号：US12010312
申请日：2008-01-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3865
摘要： A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.
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公开(公告)号：US20090187741A1
公开(公告)日：2009-07-23
申请号：US12010305
申请日：2008-01-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30145 , G06F9/30149 , G06F9/30189 , G06F9/3816 , G06F9/382 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
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公开(公告)号：US20090187740A1
公开(公告)日：2009-07-23
申请号：US12010318
申请日：2008-01-23
IPC分类号： G06F9/312
CPC分类号： G06F9/3875 , G06F9/30181 , G06F9/30185 , G06F9/30196 , G06F9/382 , G06F9/3861
摘要： In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.
摘要翻译： 在数据处理系统中，从存储器取出表示程序指令的数据，每个指令来自包括至少第一和第二组指令的多组指令中的一个指令，并且所提取的数据中的每个程序指令包括一个或多个块 被预解码，每个块表示指令的一部分。 预解码电路被配置为对块执行预解码操作。 对于来自第一组指令的指令的至少一部分和来自第二组指令的指令的至少一部分，对从存储器取出的块执行的预解码操作与该块是否被识别为代表 来自第一组指令的指令的至少一部分或来自第二组指令的指令的至少一部分。
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公开(公告)号：US09075622B2
公开(公告)日：2015-07-07
申请号：US12010318
申请日：2008-01-23
CPC分类号： G06F9/3875 , G06F9/30181 , G06F9/30185 , G06F9/30196 , G06F9/382 , G06F9/3861
摘要： In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.
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6.发明授权Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权用于处理由处理电路执行的指令的数据处理装置和方法公开(公告)号：US07925866B2
公开(公告)日：2011-04-12
申请号：US12314095
申请日：2008-12-03
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30149 , G06F9/3816 , G06F9/382 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。
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公开(公告)号：US20090187742A1
公开(公告)日：2009-07-23
申请号：US12010312
申请日：2008-01-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3865
摘要： A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.
摘要翻译： 数据处理装置设置有用于产生存储在指令高速缓存20中的预解码指令的预解码电路10.来自指令高速缓存20的预解码指令由解码电路45,50,46读取并使用 以形成用于控制与预解码指令相对应的处理操作的控制信号。 最初提取的程序指令可以属于多个指令集中的相应的指令集。 来自一个指令集的指令由预解码电路10预解码为具有共享格式的预解码指令，以表示从另一个指令集获取的相应指令的共享功能。 以这种方式，解码电路的共享部分可以相对于来自这两个不同指令集的指令的共享功能产生控制信号。
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公开(公告)号：US09223677B2
公开(公告)日：2015-12-29
申请号：US12155926
申请日：2008-06-11
CPC分类号： G06F11/348 , G06F11/3636
摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.
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公开(公告)号：US08621336B2
公开(公告)日：2013-12-31
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.
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公开(公告)号：US20100250802A1
公开(公告)日：2010-09-30
申请号：US12382939
申请日：2009-03-26
CPC分类号： G06F13/4022
摘要： A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.
摘要翻译： 提供了一种数据处理装置和方法，用于对由一个或多个从设备处理的处理电路发出的一系列访问请求进行危险检测。 一系列访问请求包括一个或多个写访问请求，每个写访问请求指定要由寻址的从设备执行的写操作，并且每个发出的写访问请求是待处理写访问请求，直到写操作已经被 寻址的从设备。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应于由处理电路发出的写入访问请求的接收，以执行更新处理以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果另一待处理写入的标识 访问请求被该更新过程覆盖，以增加其中一个计数器中的计数值。 在由所寻址的从设备完成每次写入访问请求后，更新电路执行进一步的更新处理，以从挂起的写入访问历史存储中移除该完成的写访问请求的记录。 危害检查电路然后对由处理电路发出的访问请求的至少一个子集作出响应，以引用待处理写入访问历史存储，以便确定是否发生危险状况。 更新电路使用缓冲器和计数器的组合来保持每个待处理写入访问请求的记录的方式提供了关于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。
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