公开(公告)号：US4571097A

公开(公告)日：1986-02-18

申请号：US694441

申请日：1985-01-24

申请人： Peter W. Lee ,  Gary E. Kreider ,  Ronald L. Widner

发明人： Peter W. Lee ,  Gary E. Kreider ,  Ronald L. Widner

IPC分类号： F16C19/36 ,  F16C33/60 ,  F16C33/66

CPC分类号： F16C33/667 ,  F16C19/364 ,  F16C33/605 ,  F16C33/6674 ,  F16C33/6681

摘要： A tapered roller bearing has a rib ring against which the large ends of the tapered rollers for the bearing bear to prevent those rollers from being expelled from the annular space between the tapered raceways. The rib ring includes a porous, yet rigid, core and a jacket which covers the exposed surfaces of the core, except along an abutment face at which the large end faces of the rollers contact the rib ring. Here the pores of the core are exposed. The core at one of its other faces has a groove and the jacket has a port that opens into the groove. Pressurized oil is directed through the port and into the groove, from which it flows through the pores of the core and emerges at the abutment surface where it reduces friction between the abutment surface and the roller end faces.

摘要翻译： 圆锥滚子轴承具有肋环，用于轴承的圆锥滚子的大端部能够抵靠该肋环，以防止这些辊从锥形滚道之间的环形空间排出。 肋环包括多孔但刚性的芯和覆盖芯的暴露表面的护套，除了沿着辊的大端面接触肋环的邻接面之外。 这里，核心的孔被暴露。 其另一个面上的芯具有凹槽，并且护套具有通向凹槽的开口。 加压油被引导通过端口并进入凹槽中，从而流过该芯的孔隙，并且出现在邻接表面处，从而减小邻接表面和辊端面之间的摩擦。

公开(公告)号：US08996785B2

公开(公告)日：2015-03-31

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00 ,  G11C16/32 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US08237212B2

公开(公告)日：2012-08-07

申请号：US13072281

申请日：2011-03-25

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07915092B2

公开(公告)日：2011-03-29

申请号：US12001647

申请日：2007-12-12

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： H01L21/82

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US20110072201A1

公开(公告)日：2011-03-24

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/02 ,  G11C16/06

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US20080247230A1

公开(公告)日：2008-10-09

申请号：US11483241

申请日：2006-07-07

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/06 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07149120B2

公开(公告)日：2006-12-12

申请号：US11011304

申请日：2004-12-14

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

公开(公告)号：US06714457B1

公开(公告)日：2004-03-30

申请号：US10233642

申请日：2002-09-03

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C2211/5622

摘要： In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.

摘要翻译： 在本发明中，使用通道编程操作并行地对多个MLC闪速存储器单元进行编程，通过向连接到待编程单元的位线向字线施加高正电压和正电压。 与字线电压组合的正位线电压产生足以在预定量的时间内将所需Vt电平并行编程到每个单元中的沟道电压。 使用高正字线电压打开正在编程的单元的通道，并消除潜在的击穿条件，带对隧道电流，沟道夹紧和空穴注入栅绝缘体，同时允许具有低功耗的小对称单元 和更高的耐力周期。

公开(公告)号：US06687154B2

公开(公告)日：2004-02-03

申请号：US10364033

申请日：2003-02-11

申请人： Peter W. Lee ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Fu-Chang Hsu

IPC分类号： G11C1604

CPC分类号： H01L27/1126 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115

摘要： A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

摘要翻译： 实现了存储单元装置。 存储单元器件包括具有栅极，漏极和源极的第一晶体管。 第二个晶体管具有栅极，漏极和源极。 第一晶体管漏极耦合到阵列位线。 第二晶体管源耦合到阵列源极线。 第一晶体管源耦合到第二晶体管漏极。 第一晶体管和第二晶体管包括一个闪存晶体管和一个掩模ROM晶体管。 可以读取掩模ROM晶体管的编程状态。

公开(公告)号：US06660585B1

公开(公告)日：2003-12-09

申请号：US09531787

申请日：2000-03-21

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273

摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

摘要翻译： 在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。 通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。 作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。 通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。