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    Set of three level concurrent word line bias conditions for a nor type flash memory array
    1.
    发明授权
    Set of three level concurrent word line bias conditions for a nor type flash memory array 有权
    对于闪存阵列的类型，可以设置三级并发字线偏置条件

    公开(公告)号：US06620682B1

    公开(公告)日：2003-09-16

    申请号：US09978230

    申请日：2001-10-16

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    IPC分类号： H01L21336

    CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

    摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

    摘要翻译： 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。

    3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
    2.
    发明授权
    3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell 有权
    3步写操作非易失性半导体单晶体管，非型闪存EEPROM存储单元

    公开(公告)号：US06556481B1

    公开(公告)日：2003-04-29

    申请号：US09852247

    申请日：2001-05-09

    申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Mervyn Wong

    发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Mervyn Wong

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C2216/28

    摘要： In the present invention a three step write of a nonvolatile single transistor cell is disclosed. The three steps comprise erasing, reverse programming and programming which can be applied to a plurality of cell types to produce a symmetrical design and allowing shrinkage of the cell beyond that which is possible with other cells designed to use a two step write procedure. The methodology can be applied to either N-channel or P-channel devices and can be used on various type memory cells such as “ETOX”, “NOR” type, “AND” type, and “OR” type. Erasing and programming steps increase the Vt of the cell transistor, whereas reverse programming decreases the Vt of the cell transistor. Over-erase problems are eliminated using the three step write procedure.

    摘要翻译： 在本发明中，公开了一种非易失性单晶体管单元的三步写入。 三个步骤包括擦除，反向编程和编程，其可以应用于多个单元类型以产生对称设计，并且允许单元的收缩超过设计为使用两步写入过程的其他单元可能的缩小。 该方法可应用于N沟道或P沟道器件，可用于各种类型的存储单元，例如“ETOX”，“NOR”型，“AND”型和“OR”型。 擦除和编程步骤增加了单元晶体管的Vt，而反向编程减小了单元晶体管的Vt。 使用三步写入过程可以消除过度擦除问题。

    Set of three level concurrent word line bias conditions for a NOR type flash memory array
    3.
    发明授权
    Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
    用于NOR型闪存阵列的三级并发字线偏置条件集

    公开(公告)号：US06818491B2

    公开(公告)日：2004-11-16

    申请号：US10627834

    申请日：2003-07-25

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    IPC分类号： H01L218238

    CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

    摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

    摘要翻译： 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。

    Set of three level concurrent word line bias conditions for a NOR type flash memory array
    4.
    发明授权
    Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权

    公开(公告)号：US06777292B2

    公开(公告)日：2004-08-17

    申请号：US10627183

    申请日：2003-07-25

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

    IPC分类号： H01L21336

    CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

    摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    5.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
    单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US07372736B2

    公开(公告)日：2008-05-13

    申请号：US11391662

    申请日：2006-03-28

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    8.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
    单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US07064978B2

    公开(公告)日：2006-06-20

    申请号：US10351180

    申请日：2003-01-24

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

    Node-precise voltage regulation for a MOS memory system
    9.
    发明授权
    Node-precise voltage regulation for a MOS memory system 有权
    用于MOS存储器系统的节点精确电压调节

    公开(公告)号：US6009022A

    公开(公告)日：1999-12-28

    申请号：US189109

    申请日：1998-11-09

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/30 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C16/30 ,  G11C5/147 ,  G11C8/08

    摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.

    摘要翻译： 片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压。 位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较 差分输出比较器。 用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。 该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。 该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。 该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

    Node-precise voltage regulation for a MOS memory system
    10.
    发明授权
    Node-precise voltage regulation for a MOS memory system 失效
    用于MOS存储器系统的节点精确电压调节

    公开(公告)号：US5835420A

    公开(公告)日：1998-11-10

    申请号：US884251

    申请日：1997-06-27

    申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/30 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C16/30 ,  G11C5/147 ,  G11C8/08

    摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from at least one of which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.

    摘要翻译： 片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压中的至少一个。 位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较 差分输出比较器。 用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。 该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。 该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。 该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。