公开(公告)号：US5804869A

公开(公告)日：1998-09-08

申请号：US829073

申请日：1997-03-31

申请人： Peyman Hadizad ,  Ali Salih ,  John Robert Bender ,  John David Moran

发明人： Peyman Hadizad ,  Ali Salih ,  John Robert Bender ,  John David Moran

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/58

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L2924/0002

摘要： A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.

摘要翻译： 半导体结构（10）使用设置在半导体器件中的电介质结构（14）的边缘（27）处的夹具（16）。 夹具基本上减少了介质结构或层离开下面的半导体材料（20,24）的分离或剥离。 夹具还提供了保护介电层和下面的半导体材料之间的界面免受化学或水分侵蚀的好处，无论是在后期加工还是在最终制造之后。 这种化学或水分侵袭和内部薄膜应力是导致电介质膜与下面的半导体材料分离的因素。 夹具例如用于防止在功率整流二极管中分离氮化硅或氧化物钝化与砷化镓衬底。

公开(公告)号：US07205605B2

公开(公告)日：2007-04-17

申请号：US10842393

申请日：2004-05-10

申请人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

发明人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

摘要翻译： 半导体部件包括具有沟槽（326）的半导体层（110）。 沟渠有第一面和第二面。 半导体层的一部分（713）具有导电类型和电荷密度。 半导体部件还包括沟槽中的控制电极（540,1240）。 半导体部件还包括在半导体层中并且与沟槽相邻的沟道区域（120）。 半导体部件还包括半导体层中的区域（755）。 该区域具有与半导体层的部分不同的导电类型。 该区域还具有平衡半导体层部分的电荷密度的电荷密度。

公开(公告)号：US06756273B2

公开(公告)日：2004-06-29

申请号：US09802726

申请日：2001-03-12

申请人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

发明人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

IPC分类号： H01L2100

CPC分类号： H01L29/66734 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

摘要翻译： 半导体部件包括具有沟槽（326）的半导体层（110）。 沟渠有第一面和第二面。 半导体层的一部分（713）具有导电类型和电荷密度。 半导体部件还包括沟槽中的控制电极（540,1240）。 半导体部件还包括在半导体层中并且与沟槽相邻的沟道区域（120）。 半导体部件还包括半导体层中的区域（755）。 该区域具有与半导体层的部分不同的导电类型。 该区域还具有平衡半导体层部分的电荷密度的电荷密度。

公开(公告)号：US07518185B2

公开(公告)日：2009-04-14

申请号：US11668872

申请日：2007-01-30

申请人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

发明人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

公开(公告)号：US20080006874A1

公开(公告)日：2008-01-10

申请号：US11668872

申请日：2007-01-30

申请人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

发明人： Peyman Hadizad ,  Jina Shumate ,  Ali Salih

IPC分类号： H01L29/76

CPC分类号： H01L29/66734 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

摘要翻译： 半导体部件包括具有沟槽（326）的半导体层（110）。 沟渠有第一面和第二面。 半导体层的一部分（713）具有导电类型和电荷密度。 半导体部件还包括沟槽中的控制电极（540,1240）。 半导体部件还包括在半导体层中并且与沟槽相邻的沟道区域（120）。 半导体部件还包括半导体层中的区域（755）。 该区域具有与半导体层的部分不同的导电类型。 该区域还具有平衡半导体层部分的电荷密度的电荷密度。

公开(公告)号：US5949124A

公开(公告)日：1999-09-07

申请号：US999889

申请日：1997-05-09

申请人： Peyman Hadizad ,  Zheng Shen ,  Ali Salih

发明人： Peyman Hadizad ,  Zheng Shen ,  Ali Salih

IPC分类号： H01L23/58 ,  H01L29/06

CPC分类号： H01L23/585 ,  H01L29/0661 ,  H01L2924/0002

摘要： An edge termination structure is created by forming trench structures (14) near a PN junction. The presence of the trench structures (14) extends a depletion region (13) between a doped region (12) and a body of semiconductor material or a semiconductor substrate (11) of the opposite conductivity type away from the doped region (12). This in turn forces junction breakdown to occur in the semiconductor bulk, leading to enhancement of the breakdown voltage of a semiconductor device (10). A surface of the trench structures (14) is covered with a conductive layer (16) which keeps the surface of the trench structures (14) at an equal voltage potential. This creates an equipotential surface across each of the trench structures (14) and forces the depletion region to extend laterally along the surface of semiconductor substrate (11). The conductive layers (16) are electrically isolated from an electrical contact (17) which contacts the doped region (12) and from the conductive layers (16) of neighboring trench structures (14).

摘要翻译： 通过在PN结附近形成沟槽结构（14）来产生边缘终端结构。 沟槽结构（14）的存在延伸了掺杂区域（12）和半导体材料体之间的耗尽区（13）或者与掺杂区域（12）相反的导电类型的半导体衬底（11）。 这又导致在半导体体中发生结击穿，导致半导体器件（10）的击穿电压的提高。 沟槽结构（14）的表面被导电层（16）覆盖，导电层保持沟槽结构（14）的表面处于相等的电压电位。 这产生跨越每个沟槽结构（14）的等势面，并迫使耗尽区沿着半导体衬底（11）的表面横向延伸。 导电层（16）与接触掺杂区域（12）的电触点（17）和相邻沟槽结构（14）的导电层（16）电隔离。

公开(公告)号：US20100085325A1

公开(公告)日：2010-04-08

申请号：US12568066

申请日：2009-09-28

申请人： Oliver P. King-Smith ,  Bernardus H. Smit ,  Peyman Hadizad

发明人： Oliver P. King-Smith ,  Bernardus H. Smit ,  Peyman Hadizad

IPC分类号： G06F3/045

CPC分类号： G06F3/0418 ,  G06F3/03545 ,  G06F3/0383 ,  G06F3/0416 ,  G06F3/044 ,  G06F3/046 ,  G06F2203/04104 ,  G06F2203/04105 ,  G06F2203/04106 ,  G06F2203/04108

摘要： A combination touch and transducer input system is provided, which facilitates user input into an electronic system with a finger and/or a transducer (e.g., a stylus). The system includes a transducer configured to generate an electric field, and a sensor including an array of electrodes and a controller. The transducer is configured to transmit digital data, such as pen pressure data and switch status data, to the sensor. For example, the transducer comprises electronic circuitry configured to encode the digital data in a signal for transmission to the sensor. The sensor controller is configured to operate both in a touch sensing mode and in a transducer sensing mode. During the touch sensing mode, the controller determines a position of a proximate object (e.g., a finger) by capacitively sensing the object with the array of electrodes. During the transducer sensing mode, the controller determines a position of the transducer based on a signal received by the array of electrodes from the transducer, and also receives and decodes the digital data encoded in the received signal. Digital data can be encoded in a signal using any suitable digital modulation techniques, such as a Frequency-Shift Keying (FSK) technique.

摘要翻译： 提供组合的触摸和换能器输入系统，其便于用手指和/或换能器（例如，触针）将用户输入电子系统。 该系统包括被配置为产生电场的换能器，以及包括电极阵列和控制器的传感器。 传感器配置为将数字数据（如笔压数据和开关状态数据）传输到传感器。 例如，换能器包括被配置为将数字数据编码在用于传输到传感器的信号中的电子电路。 传感器控制器被配置为在触摸感测模式和换能器感测模式下同时操作。 在触摸感测模式期间，控制器通过用电极阵列电容感测物体来确定邻近对象（例如，手指）的位置。 在换能器感测模式期间，控制器基于由换能器的电极阵列接收的信号来确定换能器的位置，并且还接收并解码在接收信号中编码的数字数据。 数字数据可以使用任何合适的数字调制技术（例如频移键控（FSK）技术）在信号中进行编码。

公开(公告)号：US07087472B2

公开(公告)日：2006-08-08

申请号：US10623392

申请日：2003-07-18

申请人： Peyman Hadizad

发明人： Peyman Hadizad

IPC分类号： H01L21/337

CPC分类号： H01L29/66856 ,  H01L29/8122

摘要： In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.

摘要翻译： 在一个实施例中，一种用于制造化合物半导体垂直FET器件的方法包括在半导体材料体中形成第一沟槽，以及在第一沟槽内形成自对准的第二沟槽以限定沟道区。 然后在第二沟槽的侧壁和底表面上形成掺杂栅极区域。 源极区域形成在沟槽结构的相对侧上。 局部栅极接触区将各个掺杂的栅极区域耦合在一起。 接触件然后形成到局部栅极接触区域，源极区域和半导体材料体的相对表面。 该方法提供了具有增强的阻挡能力的化合物半导体垂直FET结构。

公开(公告)号：US09071347B2

公开(公告)日：2015-06-30

申请号：US13590209

申请日：2012-08-21

申请人： Peyman Hadizad ,  Roupen Nahabedian ,  Scott R. Schroeder

发明人： Peyman Hadizad ,  Roupen Nahabedian ,  Scott R. Schroeder

IPC分类号： G06F15/16 ,  H04B17/00 ,  H04W8/22 ,  H04W4/00

CPC分类号： H04W4/50 ,  H04W4/80 ,  H04W8/22

摘要： An electronic device configured for transferring at least one on board application program to a second electronic device, includes a processor employing software for performing an analysis of real-time operating characteristics of the electronic device, including any anomalous operating characteristics, in relation to on board application programs in the electronic device. A communication link, coupled to the electronic device, is configured for transferring at least one onboard application program from the electronic device to the second electronic device. The transfer of the at least one onboard application program from the electronic device to the second electronic device proceeds only if the software employed by the processor validates that the at least one onboard application program in the electronic device is unlikely to degrade operating characteristics of the second electronic device.

摘要翻译： 一种被配置为将至少一个车载应用程序传送到第二电子设备的电子设备，包括使用软件的处理器，用于执行电子设备的实时操作特性的分析，包括与船上相关的任何异常操作特性 应用程序在电子设备中。 耦合到电子设备的通信链路被配置用于将至少一个板载应用程序从电子设备传送到第二电子设备。 只有当处理器使用的软件验证电子设备中的至少一个车载应用程序不太可能降低第二电子设备的操作特性时，将至少一个车载应用程序从电子设备传送到第二电子设备 电子设备。

公开(公告)号：US07038295B2

公开(公告)日：2006-05-02

申请号：US10623390

申请日：2003-07-18

申请人： Peyman Hadizad

发明人： Peyman Hadizad

IPC分类号： H01L29/00

CPC分类号： H01L27/0605 ,  H02M3/1588 ,  Y02B70/1466

摘要： In one embodiment, a dc/dc converter network (71) is described. The converter network (71) includes at least one GaAs depletion mode or normally on FET device (711, 712). The converter network (71) is a two-port system having a positive input terminal (710), a positive output terminal (730), and a negative input terminal (720) connected to a negative output terminal (740). A first GaAs depletion mode FET (711) is connected between the positive input terminal (710) and an internal node (795). A second GaAs depletion mode FET (712) is connected between the internal node (795) and the common negative terminals (720, 740). A control circuit (780) is connected gate leads of the two FETs (711, 712), to alternatively switch the devices from a current conducting mode to a current blocking mode. An inductor (760) is connected between the internal node (795) and the positive output terminal (730). The GaAs depletion mode devices provide a converter network with improved performance.

摘要翻译： 在一个实施例中，描述了dc / dc转换器网络（71）。 转换器网络（71）包括至少一个GaAs耗尽模式或通常在FET器件（711,712）上。 转换器网络（71）是具有正输入端（710），正输出端（730）和连接到负输出端（740）的负输入端（720）的双端口系统。 第一GaAs耗尽型FET（711）连接在正输入端（710）和内节点（795）之间。 第二GaAs耗尽型FET（712）连接在内部节点（795）和公共负极端子（720,740）之间。 控制电路（780）是两个FET（711,712）的栅极引线连接，以将器件交替地从电流导通模式切换到电流阻断模式。 电感器（760）连接在内部节点（795）和正极输出端子（730）之间。 GaAs耗尽模式器件提供了具有改进性能的转换器网络。