公开(公告)号：US20180040628A1

公开(公告)日：2018-02-08

申请号：US15462933

申请日：2017-03-20

申请人： Phil-ouk Nam ,  Sung-gil KIM ,  Ji-hoon CHOI ,  SeuI-ye KIM ,  Jae-young AHN ,  Hong-suk KIM

发明人： Phil-ouk Nam ,  Sung-gil KIM ,  Ji-hoon CHOI ,  SeuI-ye KIM ,  Jae-young AHN ,  Hong-suk KIM

IPC分类号： H01L27/11582 ,  H01L29/78 ,  H01L27/11556

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7827

摘要： A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.

公开(公告)号：US20180122907A1

公开(公告)日：2018-05-03

申请号：US15646184

申请日：2017-07-11

申请人： Ji-hoon CHOI ,  Hong-suk KIM ,  Sung-gil KIM ,  Phil-ouk NAM ,  Seul-ye KIM ,  Han-jin LIM ,  Jae-young AHN

发明人： Ji-hoon CHOI ,  Hong-suk KIM ,  Sung-gil KIM ,  Phil-ouk NAM ,  Seul-ye KIM ,  Han-jin LIM ,  Jae-young AHN

IPC分类号： H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L29/1037 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.

公开(公告)号：US20130270631A1

公开(公告)日：2013-10-17

申请号：US13796394

申请日：2013-03-12

申请人： Bi-o KIM ,  Jin-tae NOH ,  Chang-woo SUN ,  Jae-young AHN ,  Seung-hyun LIM ,  Ki-hyun HWANG

发明人： Bi-o KIM ,  Jin-tae NOH ,  Chang-woo SUN ,  Jae-young AHN ,  Seung-hyun LIM ,  Ki-hyun HWANG

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/7827

摘要： A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.