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106 条记录 (耗时 0.029 秒)

    Method for enabling concurrent misses in a cache memory
    1.
    发明授权
    Method for enabling concurrent misses in a cache memory 失效
    启用缓存中的并发错误的方法

    公开(公告)号：US5636364A

    公开(公告)日：1997-06-03

    申请号：US347972

    申请日：1994-12-01

    申请人： Philip G. Emma ,  Joshua W. Knight, III ,  Thomas R. Puzak

    发明人： Philip G. Emma ,  Joshua W. Knight, III ,  Thomas R. Puzak

    IPC分类号： G06F12/08 ,  G06F13/14

    CPC分类号： G06F12/0806 ,  G06F12/0859

    摘要： In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

    摘要翻译： 在缓存到存储器接口中，一种用于对单个总线进行时分多路复用以允许并发处理多个未命中的方法和方法。 如果该处理器具有非阻塞高速缓存和/或进行推测性预取，或者可能由共享总线配置中的多个处理器产生，则单个处理器可能会产生多个未命中。

    Computer processing unit employing a separate millicode branch history table
    2.
    发明授权
    Computer processing unit employing a separate millicode branch history table 失效
    计算机处理单元采用单独的millicode分支历史表

    公开(公告)号：US5634119A

    公开(公告)日：1997-05-27

    申请号：US369441

    申请日：1995-01-06

    申请人： Philip G. Emma ,  Joshua W. Knight, III ,  Thomas R. Puzak ,  James R. Robinson ,  A. James Van Norstrand, Jr.

    发明人： Philip G. Emma ,  Joshua W. Knight, III ,  Thomas R. Puzak ,  James R. Robinson ,  A. James Van Norstrand, Jr.

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3806 ,  G06F9/3017

    摘要： A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table.The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.

    摘要翻译： 计算机处理系统包括存储属于第一指令集架构的指令的第一存储器和存储属于第二指令集架构的指令的第二存储器。 指令缓冲器耦合到第一和第二存储器，用于存储由处理器单元执行的指令。 该系统以两种模式之一运行。 在第一模式中，根据存储在第一分支历史表中的数据，将指令从第一存储器提取到指令缓冲器中。 在第二模式中，根据存储在第二分支历史表中的数据，将指令从第二存储器提取到指令缓冲器中。 第一指令集架构可以是系统级指令，并且第二指令集架构可以是例如定义复杂系统级指令和/或模拟第三指令集体系结构的毫指令指令。

    Posting out-of-sequence fetches
    3.
    发明授权
    Posting out-of-sequence fetches 失效
    发布超时取款

    公开(公告)号：US4991090A

    公开(公告)日：1991-02-05

    申请号：US51792

    申请日：1987-05-18

    申请人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

    发明人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

    IPC分类号： G06F9/38 ,  G06F15/16 ,  G06F15/177

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3834

    摘要： Monitoring apparatus is provided to allow out-of-sequence fetching of operands while preserving the appearance of in-sequence fetching to the processor of a computer. The key elements include a stack (119) of N entries holding the addresses of the last M, where M is less than or equal to N, out-of-sequence fetches. A comparator (103) is provided for comparing addresses in the stack with a test address. This test address is supplied via an OR gate (107) as either store addresses or cross-invalidate addresses, the latter being for a multiprocessor system. The addresses in the stack that compare with the test address are set as invalid. In addition, all addresses in the stack are set as invalid on the occurrence of a cache miss or serializing instruction. Finally, a select and check entry function (113) associates an address in the stack with the instruction it represents and deletes the address from the stack when the instruction is handled in its proper sequence.

    Method and apparatus for prefetching branch history information
    8.
    发明授权
    Method and apparatus for prefetching branch history information 失效
    用于预取分支历史信息的方法和装置

    公开(公告)号：US07493480B2

    公开(公告)日：2009-02-17

    申请号：US10197714

    申请日：2002-07-18

    申请人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

    发明人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3806

    摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

    摘要翻译： 通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善 处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。 在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。 实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

    Simultaneous prediction of multiple branches for superscalar processing
    9.
    发明授权
    Simultaneous prediction of multiple branches for superscalar processing 失效
    同时预测超标量处理的多个分支

    公开(公告)号：US5434985A

    公开(公告)日：1995-07-18

    申请号：US928851

    申请日：1992-08-11

    申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak

    发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： System and method for predicting a multiplicity of future branches simultaneously (parallel) from an executing program, to enable the simultaneous fetching of multiple disjoint program segments. Additionally, the present invention detects divergence of incorrect branch predictions and provides correction for such divergence without penalty. By predicting an entire sequence of branches in parallel, the present invention removes restrictions that decoding of multiple instructions in a superscalar environment must be limited to a single branch group. As a result, the speed of today's superscalar processors can be significantly increased. The present invention includes three main embodiments: (1) the first embodiment is directed to a simplex multibranch prediction device, that can predict a plurality of branch groups in one cycle and provide early detection of wrong predictions; (2) the second embodiments is directed to a duplex multibranch prediction device that can detect divergence in a predicted stream, and provide redirection (correction) within the stream; and (3) the third embodiment is directed to an n-plex multibranch prediction device, that can predict n multiplicity of branch predictions simultaneously and provide an early detection of wrong predictions as well as correction of wrong predictions.

    摘要翻译： 用于从执行程序同时（并行）预测多个未来分支的系统和方法，以使得能够同时获取多个不相交的程序段。 此外，本发明检测不正确分支预测的发散，并且对这种发散提供校正而没有惩罚。 通过并行地预测整个分支序列，本发明消除了限制在超标量环境中多个指令的解码必须限于单个分支组的限制。 因此，今天的超标量处理器的速度可以大大提高。 本发明包括三个主要实施例：（1）第一实施例涉及可以在一个周期内预测多个分支组并提供错误预测的早期检测的单工多分支预测装置; （2）第二实施例涉及可以检测预测流中的发散并且在流内提供重定向（校正）的双工多分支预测设备; 和（3）第三实施例涉及n-plex多分支预测装置，其可以同时预测分支预测的多个，并提供错误预测的早期检测以及错误预测的校正。