公开(公告)号：US20080132191A1

公开(公告)日：2008-06-05

申请号：US11881019

申请日：2007-07-25

申请人： Philip Quinlan ,  Miguel Chanca ,  Hyman Shanan ,  Vincent Foley

发明人： Philip Quinlan ,  Miguel Chanca ,  Hyman Shanan ,  Vincent Foley

IPC分类号： H04B1/10

CPC分类号： H03D7/18 ,  H04B1/28

摘要： Image rejection calibration includes initializing the calibration mode by applying to quadrature mixers, in place of the wanted RF input, an RF source in the frequency range of the wanted RF input, sensing the power output from the poly-phase filter, developing gain adjust and phase adjust correction values in response to the power output and adjusting in accordance with the correction values the gain of the quadrature signals from the quadrature mixers to the poly-phase filter and the phase of local oscillator quadrature signals from the local oscillator to the quadrature mixers to reduce the power output.

摘要翻译： 图像抑制校准包括通过应用正交混频器代替所需的RF输入，在所需RF输入的频率范围内的RF源，感测来自多相滤波器的功率输出，显影增益调整和 响应于功率输出的相位调整校正值，并且根据校正值来调整来自正交混频器到多相滤波器的正交信号的增益以及从本地振荡器到正交混频器的本地振荡器正交信号的相位 以减少功率输出。

公开(公告)号：US08358993B2

公开(公告)日：2013-01-22

申请号：US11881019

申请日：2007-07-25

申请人： Philip Quinlan ,  Miguel Chanca ,  Hyman Shanan ,  Vincent Foley

发明人： Philip Quinlan ,  Miguel Chanca ,  Hyman Shanan ,  Vincent Foley

IPC分类号： H04B1/18 ,  H04B1/10

CPC分类号： H03D7/18 ,  H04B1/28

摘要： Image rejection calibration includes initializing the calibration mode by applying to quadrature mixers, in place of the wanted RF input, an RF source in the frequency range of the wanted RF input, sensing the power output from the poly-phase filter, developing gain adjust and phase adjust correction values in response to the power output and adjusting in accordance with the correction values the gain of the quadrature signals from the quadrature mixers to the poly-phase filter and the phase of local oscillator quadrature signals from the local oscillator to the quadrature mixers to reduce the power output.

摘要翻译： 图像抑制校准包括通过应用正交混频器代替所需的RF输入，在所需RF输入的频率范围内的RF源，感测来自多相滤波器的功率输出，显影增益调整和 响应于功率输出的相位调整校正值，并且根据校正值来调整来自正交混频器到多相滤波器的正交信号的增益以及从本地振荡器到正交混频器的本地振荡器正交信号的相位 以减少功率输出。

公开(公告)号：US08238865B2

公开(公告)日：2012-08-07

申请号：US12576630

申请日：2009-10-09

申请人： Miguel Chanca ,  Ronan Casey ,  Patrick Crowley ,  Muhammad Khan ,  Philip Quinlan

发明人： Miguel Chanca ,  Ronan Casey ,  Patrick Crowley ,  Muhammad Khan ,  Philip Quinlan

IPC分类号： H04B1/10

CPC分类号： H04B1/30

摘要： Embodiments of a system for calibrating the image rejection of a receiver include an image-rejection correction circuit that modifies the gain and phase of a first channel of a baseband image signal. The image-rejection correction circuit may include a summing circuit and first and second variable-gain elements. In one implementation, a filter receives a corrected first channel from the image-rejection correction circuit and an unmodified second channel of the image signal, while a controller analyzes power measured at the output of the filter, and adjusts the variable-gain elements to reduce the power of the image signal.

摘要翻译： 用于校准接收机的图像抑制的系统的实施例包括修改基带图像信号的第一通道的增益和相位的图像拒绝校正电路。 图像抑制校正电路可以包括求和电路和第一和第二可变增益元件。 在一个实现中，滤波器从图像抑制校正电路和图像信号的未修改的第二通道接收校正的第一通道，而控制器分析在滤波器的输出处测量的功率，并且调整可变增益元件以减少 图像信号的功率。

公开(公告)号：US20110086605A1

公开(公告)日：2011-04-14

申请号：US12576630

申请日：2009-10-09

申请人： Miguel Chanca ,  Ronan Casey ,  Patrick Crowley ,  Muhammad Khan ,  Philip Quinlan

发明人： Miguel Chanca ,  Ronan Casey ,  Patrick Crowley ,  Muhammad Khan ,  Philip Quinlan

IPC分类号： H04B1/10

CPC分类号： H04B1/30

摘要： Embodiments of a system for calibrating the image rejection of a receiver include an image-rejection correction circuit that modifies the gain and phase of a first channel of a baseband image signal. The image-rejection correction circuit may include a summing circuit and first and second variable-gain elements. In one implementation, a filter receives a corrected first channel from the image-rejection correction circuit and an unmodified second channel of the image signal, while a controller analyzes power measured at the output of the filter, and adjusts the variable-gain elements to reduce the power of the image signal.

摘要翻译： 用于校准接收机的图像抑制的系统的实施例包括修改基带图像信号的第一通道的增益和相位的图像拒绝校正电路。 图像抑制校正电路可以包括求和电路和第一和第二可变增益元件。 在一个实现中，滤波器从图像抑制校正电路和图像信号的未修改的第二通道接收校正的第一通道，而控制器分析在滤波器的输出处测量的功率，并且调整可变增益元件以减少 图像信号的功率。

公开(公告)号：US5583713A

公开(公告)日：1996-12-10

申请号：US279299

申请日：1994-07-22

申请人： Peter Real ,  Mairtin Walsh ,  Kenneth Deevy ,  Patrick Griffin ,  Philip Quinlan

发明人： Peter Real ,  Mairtin Walsh ,  Kenneth Deevy ,  Patrick Griffin ,  Philip Quinlan

IPC分类号： G01N33/53 ,  G01N33/569 ,  G01N33/68 ,  G11B5/596 ,  G11B5/09

CPC分类号： G01N33/56972 ,  G01N33/5308 ,  G01N33/6866 ,  G01N33/6869 ,  G01N33/6872

摘要： A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes an input terminal for sequentially receiving a plurality of input signal bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminal, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. An ADC, coupled to the demodulation circuitry, sequentially converts each demodulated signal. The ADC converts a first demodulated signal corresponding to the first of the plurality of input signal bursts before the demodulation circuitry completes demodulating the next of the plurality of input signal bursts. In a preferred embodiment, the ADC converts a demodulated signal corresponding to a first input signal burst while the demodulation circuitry demodulates a signal corresponding to a second, and subsequent, input signal burst. Thus, a pipelined demodulation and conversion scheme is disclosed in which time delays between demodulation and conversion are reduced. In the preferred embodiment, the demodulation circuitry includes area detect circuitry having an integration circuit and a single track-and-hold amplifier.

摘要翻译： 提供了一种用于控制磁盘驱动器中读/写磁头的位置的伺服系统。 伺服系统包括用于顺序地接收突发模式的多个输入信号突发的输入端，其中输入信号突发包括头的位置信息。 耦合到输入端的解调电路对每个输入信号脉冲串进行顺序解调，并提供每个脉冲串的解调信号。 耦合到解调电路的ADC顺序地转换每个解调信号。 在解调电路完成解调多个输入信号突发中的下一个之前，ADC转换对应于多个输入信号突发中的第一个的第一解调信号。 在优选实施例中，ADC解调对应于第一输入信号脉冲串的解调信号，同时解调电路解调对应于第二和随后的输入信号脉冲串的信号。 因此，公开了一种流水线解调和转换方案，其中解调和转换之间的时间延迟减小。 在优选实施例中，解调电路包括具有积分电路和单个跟踪和保持放大器的区域检测电路。

公开(公告)号：US06522705B1

公开(公告)日：2003-02-18

申请号：US09260477

申请日：1999-03-01

申请人： Thomas Conway ,  Philip Quinlan

发明人： Thomas Conway ,  Philip Quinlan

IPC分类号： H03D100

CPC分类号： H04L1/0054 ,  H04L25/497

摘要： The invention provides an apparatus for decoding a coded digital data sequence. The apparatus includes a first Viterbi decoder of a first response type, a first filter and a second filter. The first and second filters are coupled to receive decoded sequences from the first Viterbi decoder. The first Viterbi decoder generates a first decoded sequence from the coded digital data sequence. The first and second filters generate respective first and second error signals in response to receiving the first decoded sequence. The first and second error sequences indicate differences between the first decoded sequence and second and third decoded sequences, respectively. The second and third decoded sequences are probable sequences produced by Viterbi decoders of respective second and third response types in response to receiving the coded digital data sequence.

摘要翻译： 本发明提供一种用于对编码的数字数据序列进行解码的装置。 该装置包括第一响应类型的第一维特比解码器，第一滤波器和第二滤波器。 第一和第二滤波器被耦合以从第一维特比解码器接收解码序列。 第一维特比解码器从编码数字数据序列产生第一解码序列。 响应于接收到第一解码序列，第一和第二滤波器产生相应的第一和第二误差信号。 第一和第二错误序列分别指示第一解码序列和第二和第三解码序列之间的差异。 响应于接收编码的数字数据序列，第二和第三解码序列是由相应的第二和第三响应类型的维特比解码器产生的可能序列。

公开(公告)号：US20050089120A1

公开(公告)日：2005-04-28

申请号：US10935545

申请日：2004-09-07

申请人： Philip Quinlan ,  Kenneth Mulvaney ,  Patrick Crowley ,  William Hunt

发明人： Philip Quinlan ,  Kenneth Mulvaney ,  Patrick Crowley ,  William Hunt

IPC分类号： G01R23/00 ,  H04L27/14 ,  H04L27/156 ,  H04L27/22

CPC分类号： H04L27/1525 ,  H03D3/007 ,  H03D3/02 ,  H04L27/144 ,  H04L27/156

摘要： An FSK demodulator system with tunable spectral shaping including a pair of quadri-correlators responsive to first and second quadrature signals, one of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at even integer multiples of the frequency deviation and for resolving the modulated FSK data represented by the quadrature signals and the other of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at odd integer multiples of the deviation frequency and for resolving the modulated FSK data represented by the quadrature signals, and a delay control circuit for setting a delay to each of the pair of quadri-correlators to control the first and second signals representative of the frequency deviation of the quadrature signals derived by each of the pair of quadri-correlators and generate a tuned spectral response at both even and odd integer multiples of the frequency deviation.

摘要翻译： FSK解调器系统，其具有可调频谱整形，其包括响应于第一和第二正交信号的一对四相关器，所述对中的一个导出表示正交频率的频率偏移的偶数倍的频率偏差的第一和第二信号， 用于解析由正交信号表示的调制的FSK数据，另一个导出代表偏差频率的奇整数倍的正交信号的频率偏差的第一和第二信号，并且用于分解由正交信号表示的调制的FSK数据 信号，以及延迟控制电路，用于对所述一对四相关器中的每一个设置延迟，以控制表示由所述一对四相关器中的每一个导出的正交信号的频率偏差的第一和第二信号，并产生调谐 在频率d的偶数和奇数整数倍的频谱响应 逃避

公开(公告)号：US5627537A

公开(公告)日：1997-05-06

申请号：US342769

申请日：1994-11-21

申请人： Philip Quinlan ,  Kenneth T. Deevy

发明人： Philip Quinlan ,  Kenneth T. Deevy

IPC分类号： H03M1/68 ,  H03M1/76

CPC分类号： H03M1/685 ,  H03M1/765

摘要： A differential string DAC is provided including a coarse DAC which includes a plurality of coarse resistors connected in series between first and second reference voltage leads. A positive sub-DAC includes a plurality of positive sub-DAC cells, each positive sub-DAC cell including a multitude of series-connected fine resistors. A negative sub-DAC includes a plurality of negative sub-DAC cells, each negative sub-DAC cell including a multitude of series-connected fine resistors. Each coarse resistor is electrically connected in parallel with one positive sub-DAC cell and one negative sub-DAC cell. The positive sub-DAC cell and negative sub-DAC cell are substantially symmetrically disposed about the corresponding coarse resistor. Due to the differential arrangement and symmetrical layout of the DAC, INL errors due to process gradients in one direction across the DAC are greatly reduced. Process gradients in a second orthogonal direction are not of great concern as they cause much smaller INL errors.

摘要翻译： 提供了一种差分串DAC，其包括粗略DAC，其包括串联连接在第一和第二参考电压引线之间的多个粗电阻。 正的副DAC包括多个正的sub-DAC单元，每个正的副DAC单元包括多个串联的精细电阻。 负的副DAC包括多个负的副DAC单元，每个负的Sub-DAC单元包括多个串联的精细电阻。 每个粗电阻器与一个正的副DAC电池和一个负的Sub-DAC电池并联电连接。 正的sub-DAC单元和负的sub-DAC单元基本对称地布置在相应的粗略电阻周围。 由于DAC的差分布置和对称布局，大大减少了由DAC处的一个方向上的工艺梯度引起的INL误差。 在第二正交方向上的处理梯度不是很大的关注，因为它们导致更小的INL误差。

公开(公告)号：US20050137815A1

公开(公告)日：2005-06-23

申请号：US10937030

申请日：2004-09-09

申请人： Philip Quinlan ,  Kenneth Mulvaney ,  Patrick Crowley ,  William Hunt

发明人： Philip Quinlan ,  Kenneth Mulvaney ,  Patrick Crowley ,  William Hunt

IPC分类号： G01R23/00 ,  H04L27/14 ,  H04L27/156 ,  H04L27/22

CPC分类号： H04L27/1525 ,  H03D3/007 ,  H03D3/02 ,  H04L27/144 ,  H04L27/156

摘要： A digital frequency measurement system including first and second digital differentiators responsive to first and second digital quadrature signals representative of first and second quadrature modulated input signals that represent binary data having a center frequency equal to a predetermined IF frequency for generating first and second differentiated signals, first and second processing circuits responsive to the first and second digital quadrature signals representative of the modulated input signals and the first and second differentiated signals for multiplying the first differentiated signal by the second quadrature digital representation of the input signals and multiplying the second differentiated signal by the first quadrature digital representation of the input signals to provide first and second multiplied signals, a combining circuit responsive to the first and second multiplied signals for generating a density signal having a pulse density proportional to the frequency of the input signals, a digital filter responsive to the density signal for providing an output signal representing the average value of the pulse density, and an envelope detector circuit responsive to the output signal for determining the midpoint of the maximum and minimum signal level representative of the input signals and providing a digital signal that represents the center frequency of the input signals.

摘要翻译： 一种数字频率测量系统，包括响应于代表第一和第二正交调制输入信号的第一和第二数字正交信号的第一和第二数字微分器，所述第一和第二正交调制输入信号表示具有等于预定IF频率的中心频率的二进制数据，用于产生第一和第二微分信号， 响应于表示调制输入信号的第一和第二数字正交信号的第一和第二处理电路以及用于将第一微分信号乘以输入信号的第二正交数字表示的第一和第二微分信号，并将第二微分信号乘以 输入信号的第一正交数字表示以提供第一和第二相乘信号，组合电路响应于第一和第二相乘信号，用于产生具有与频率o成比例的脉冲密度的浓度信号 f输入信号，响应于密度信号的数字滤波器，用于提供表示脉冲密度的平均值的输出信号;以及包络检测器电路，响应于输出信号，用于确定表示最大和最小信号电平的中点 输入信号并提供表示输入信号的中心频率的数字信号。

公开(公告)号：US5768320A

公开(公告)日：1998-06-16

申请号：US523648

申请日：1995-09-05

申请人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

发明人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

IPC分类号： G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/09

摘要： A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

摘要翻译： 用于实现PR4和更高阶PRML信号的读取系统包括：连续时间可编程滤波器，用于从存储介质接收表示二进制信号的读取信号，并将读取信号整形为PR4形读取信号; 响应于连续时间可编程滤波器的模拟有限脉冲响应（AFIR）滤波器，用于将PR4形读取信号采样并形成为PR4形多电平读信号; 响应于AFIR滤波器的模数转换器，用于将PR4形多级读取信号从模拟转换成数字; 响应于所述模数转换器的数据序列滤波器，用于将所述PR4形多级数字读信号转换成预定顺序PRML信号; 以及响应于数据序列滤波器的维特比检测器，用于检测来自预定顺序PRML信号的二进制信号。