公开(公告)号：US5768320A

公开(公告)日：1998-06-16

申请号：US523648

申请日：1995-09-05

申请人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

发明人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

IPC分类号： G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/09

摘要： A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

摘要翻译： 用于实现PR4和更高阶PRML信号的读取系统包括：连续时间可编程滤波器，用于从存储介质接收表示二进制信号的读取信号，并将读取信号整形为PR4形读取信号; 响应于连续时间可编程滤波器的模拟有限脉冲响应（AFIR）滤波器，用于将PR4形读取信号采样并形成为PR4形多电平读信号; 响应于AFIR滤波器的模数转换器，用于将PR4形多级读取信号从模拟转换成数字; 响应于所述模数转换器的数据序列滤波器，用于将所述PR4形多级数字读信号转换成预定顺序PRML信号; 以及响应于数据序列滤波器的维特比检测器，用于检测来自预定顺序PRML信号的二进制信号。

公开(公告)号：US5646968A

公开(公告)日：1997-07-08

申请号：US560013

申请日：1995-11-17

申请人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

发明人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099 ,  H03L7/14 ,  H03D3/24

CPC分类号： H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0996 ,  H03L7/14

摘要： A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

摘要翻译： 动态相位选择器锁相环电路包括：A / D转换器，用于接收要采样的输入; 相位检测电路，用于确定输入信号和时钟信号之间的相位误差; 时钟电路，响应相位检测电路，用于将时钟信号提供给A / D转换器，用于对输入信号的采样进行定时; 所述时钟电路包括具有多个延迟抽头的延迟电路; 以及相位选择器电路，响应于相位检测电路，用于从时钟电路初始地将时钟信号选通到A / D转换器，并使得其中一个延迟抽头能够动态地调整时钟信号的相位并减少初始 相位误差。

公开(公告)号：US5495512A

公开(公告)日：1996-02-27

申请号：US314894

申请日：1994-09-29

申请人： Janos Kovacs ,  Ronald Kroesen

发明人： Janos Kovacs ,  Ronald Kroesen

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03D3/24

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/04

摘要： A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

摘要翻译： 锁相环系统或其其它二阶反馈系统，其固有频率与其输出和其阻尼因子保持不变包括具有缩放误差缩放通道的滤波器电路，用于积分误差的积分通道和用于积分误差的积分通道 组合缩放误差和积分误差; 积分器电路，响应于求和电路产生输出信号，积分器电路的增益与其输出信号成比例; 以及控制电路，用于控制与输出信号成比例的积分通道的增益，并保持恒定的单位增益频率和反馈系统的零频率的乘积的比例并缩放，以保持阻尼因子的恒定并缩放 反馈系统的固有频率分别与输出信号。

公开(公告)号：US5414390A

公开(公告)日：1995-05-09

申请号：US304248

申请日：1994-09-12

申请人： Janos Kovacs ,  Ronald Kroesen

发明人： Janos Kovacs ,  Ronald Kroesen

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/07 ,  G11B20/10 ,  H03L7/10 ,  H03L7/18

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/04

摘要： A center frequency controlled phase locked loop system includes a primary phase locked loop having a first voltage controlled oscillator including a first voltage to current converter whose output current drives a first current controlled oscillator to produce the primary clock signal to be locked onto an input signal; a second phase locked loop having a second voltage controlled oscillator including a second voltage to current converter whose output current drives a second current controlled oscillator to produce the synthesized clock signal whose frequency is approximately that of the input signal or integral multiple thereof; and a current copier circuit for copying the output current from the second voltage to current converter and delivering it to the first current controlled oscillator to maintain the center frequency of the first voltage controlled oscillator at approximately the output frequency of the synthesized clock signal.

摘要翻译： 中心频率控制锁相环系统包括主锁相环，其具有第一压控振荡器，该第一压控振荡器包括第一电压 - 电流转换器，其输出电流驱动第一电流控制振荡器以产生待锁定到输入信号上的主时钟信号; 第二锁相环具有包括第二电压/电流转换器的第二压控振荡器，所述第二压控振荡器的输出电流驱动第二电流控制振荡器以产生频率大约为输入信号或其整数倍的合成时钟信号; 以及当前的复印机电路，用于将输出电流从第二电压复制到电流转换器，并将其传送到第一电流控制振荡器，以将第一压控振荡器的中心频率保持在合成时钟信号的输出频率的近似值。

公开(公告)号：US06373841B1

公开(公告)日：2002-04-16

申请号：US09102205

申请日：1998-06-22

申请人： Dave Goh ,  Paul Chou ,  Leena Sansguiri ,  Ronald Kroesen ,  Nandakumar Natarajan ,  John A. Dilley ,  Marcos Frid ,  Robert H. Hyerle ,  Arne Luhrs ,  Chandrasekar Venkatraman

发明人： Dave Goh ,  Paul Chou ,  Leena Sansguiri ,  Ronald Kroesen ,  Nandakumar Natarajan ,  John A. Dilley ,  Marcos Frid ,  Robert H. Hyerle ,  Arne Luhrs ,  Chandrasekar Venkatraman

IPC分类号： H04J302

CPC分类号： H04L41/046 ,  H04L41/0893 ,  H04L41/22 ,  H04L67/02

摘要： A chip for a device such as a computer includes a media access controller and an embedded processor. The embedded processor is programmed to function as a web server and provide network manageability information to a network manager. The embedded processor is also programmed to function as a LAN controller. When a packet is received by the media access controller, the embedded processor examines a destination address of the packet and routes the packet to an appropriate end point. Packets having a first unique destination address are routed to a host interface (and eventually to a host processor), and packets having a second unique address are routed to the embedded processor-functioning-as-web server. Thus, the chip allows network management and local area network communications to be performed over a single physical interface.

摘要翻译： 用于诸如计算机的设备的芯片包括媒体访问控制器和嵌入式处理器。 嵌入式处理器被编程为用作Web服务器并向网络管理器提供网络管理信息。 嵌入式处理器也被编程为作为LAN控制器。 当媒体接入控制器接收到分组时，嵌入式处理器检查分组的目的地址并将分组路由到适当的终点。 具有第一唯一目的地地址的分组被路由到主机接口（并且最终到主处理器），并且具有第二唯一地址的分组被路由到嵌入式处理器功能的web服务器。 因此，芯片允许通过单个物理接口执行网络管理和局域网通信。

公开(公告)号：US6067655A

公开(公告)日：2000-05-23

申请号：US919868

申请日：1997-08-28

申请人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

发明人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

IPC分类号： H04R3/02 ,  H03M13/00

CPC分类号： H04R3/02

摘要： A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.

摘要翻译： 突发错误限制符号检测器系统包括符号检测器电路，其响应于截取的采样信号，用于参考至少一个预选参考电平来检测以截断的采样信号编码的二进制符号; 反馈均衡器电路，用于提供用于消除输入信号中的不需要的采样的反馈均衡器信号; 响应于输入信号和反馈均衡器信号的加法电路，用于将截断的采样信号提供给符号检测器电路; 以及反馈抑制器电路，其响应于所述截断的样本在所述预选参考电平的预定范围内，以抑制所述反馈均衡器信号，以防止边缘检测到的二进制符号有助于消除所述输入信号中的不需要的采样。