公开(公告)号：US07898008B2

公开(公告)日：2011-03-01

申请号：US11779681

申请日：2007-07-18

Applicant: Piero Giorgio Fallica ,  Roberto Modica

Inventor： Piero Giorgio Fallica ,  Roberto Modica

IPC: H01L21/70

CPC classification number: H01L21/84 ,  H01L21/82285 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/7317 ,  H01L29/732

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract translation: 双极器件集成在有源层中，其中限定沟槽包围容纳互补类型的双极晶体管的相应有源区域。 每个活动区容纳埋层; 在掩埋层的顶部延伸的阱区; 在所述装置的表面和所述阱区之间延伸的顶部沉降片区域; 在阱区域的顶部延伸并且相对于顶部沉降片区域横向延伸的掩埋收集器区域; 基部区域，相对于顶部沉降片区域横向延伸在埋藏的收集器区域的顶部上; 以及在基极区域内延伸的发射极区域。 互补晶体管的同源区具有相似的掺杂水平，通过外延层的离子注入获得，其中在生长期间添加的掺杂剂的浓度非常低，可能为零。

公开(公告)号：US20080017895A1

公开(公告)日：2008-01-24

申请号：US11779681

申请日：2007-07-18

Applicant: Piero Giorgio Fallica ,  Roberto Modica

Inventor： Piero Giorgio Fallica ,  Roberto Modica

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L21/82285 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/7317 ,  H01L29/732

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract translation: 双极器件集成在有源层中，其中限定沟槽包围容纳互补类型的双极晶体管的相应有源区域。 每个活动区容纳埋层; 在掩埋层的顶部延伸的阱区; 在所述装置的表面和所述阱区之间延伸的顶部沉降片区域; 在阱区域的顶部延伸并且相对于顶部沉降片区域横向延伸的掩埋收集器区域; 基部区域，相对于顶部沉降片区域横向延伸在埋藏的收集器区域的顶部上; 以及在基极区域内延伸的发射极区域。 互补晶体管的同源区具有相似的掺杂水平，通过外延层的离子注入获得，其中在生长期间添加的掺杂剂的浓度非常低，可能为零。

公开(公告)号：US20060194408A1

公开(公告)日：2006-08-31

申请号：US11339815

申请日：2006-01-24

Applicant: Salvatore Leonardi ,  Roberto Modica

Inventor： Salvatore Leonardi ,  Roberto Modica

IPC: H01L21/76

CPC classification number: H01L23/544 ,  H01L21/32 ,  H01L21/76286 ,  H01L21/8222 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/8249 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7824 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.

Abstract translation: 一种制造电子半导体器件的方法，其中SOI晶片由半导体材料的底层，绝缘层和半导体材料顶层形成，堆叠在彼此之上; 对准标记形成在顶层中; 形成与对准标记对准的注入掩埋区域; 在顶层的顶部形成硬掩模，以将其对准对准标记; 使用硬掩模，选择性地去除顶层，以形成延伸到绝缘层的沟槽; 在沟槽中存在横向绝缘区域，其与绝缘层相邻并且与绝缘层隔开半导体材料的绝缘阱; 并且电子部件形成在顶层中。

公开(公告)号：US07960244B2

公开(公告)日：2011-06-14

申请号：US11339815

申请日：2006-01-24

Applicant: Salvatore Leonardi ,  Roberto Modica

Inventor： Salvatore Leonardi ,  Roberto Modica

IPC: H01L21/76

CPC classification number: H01L23/544 ,  H01L21/32 ,  H01L21/76286 ,  H01L21/8222 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/8249 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7824 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.

Abstract translation: 一种制造电子半导体器件的方法，其中SOI晶片由半导体材料的底层，绝缘层和半导体材料顶层形成，堆叠在彼此之上; 对准标记形成在顶层中; 形成与对准标记对准的注入掩埋区域; 在顶层的顶部形成硬掩模，以将其对准对准标记; 使用硬掩模，选择性地去除顶层，以形成延伸到绝缘层的沟槽; 在沟槽中存在横向绝缘区域，其与绝缘层相邻并且与绝缘层隔开半导体材料的绝缘阱; 并且电子部件形成在顶层中。

公开(公告)号：US20060125049A1

公开(公告)日：2006-06-15

申请号：US11333114

申请日：2006-01-17

Applicant: Salvatore Leonardi ,  Roberto Modica

Inventor： Salvatore Leonardi ,  Roberto Modica

IPC: H01L29/00

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract translation: 一种电阻结构，其集成在半导体衬底中并且具有完全被介电区域包围的适当掺杂的多晶硅区域，使得该电阻结构与联合地集成在该半导体衬底中的其它部件电隔离。

公开(公告)号：US06888213B2

公开(公告)日：2005-05-03

申请号：US10444102

申请日：2003-05-22

Applicant: Salvatore Leonardi ,  Roberto Modica ,  Giuseppe Arena

Inventor： Salvatore Leonardi ,  Roberto Modica ,  Giuseppe Arena

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Abstract translation: 通过在其中集成介电沟槽结构，在硅层中形成介电绝缘结构。 电介质沟槽结构限定了将半导体器件集成在其中的绝缘阱。 电介质沟槽结构在完全被电介质区域包围的中空区域上。 电介质区域也形成电介质沟槽结构的侧绝缘体。 电介质沟槽结构被多个点中断，以限定用于绝缘阱的多个侧支撑区域。

公开(公告)号：US06614094B2

公开(公告)日：2003-09-02

申请号：US09747167

申请日：2000-12-21

Applicant: Salvatore Leonardi ,  Roberto Modica

Inventor： Salvatore Leonardi ,  Roberto Modica

IPC: H01L2900

CPC classification number: H01L27/10861 ,  H01L28/40 ,  H01L29/66181

Abstract: A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

Abstract translation: 在由掩埋氧化物层和掩埋掺杂层覆盖的半导体衬底区域中制造的垂直电容器结构以及包括与掩埋掺杂层接触的沉降片掺杂区的半导体层，其中形成氧化物沟槽结构 ，该氧化物沟槽结构填充有适当掺杂的多晶硅，以与沉降片区域组合产生垂直电容器结构的板，其中氧化物沟槽结构在其间形成电介质。 还提供了一种从包括半导体衬底，掩埋氧化物层和掩埋掺杂层的结构坯料开始积分垂直电容器结构的工艺。