公开(公告)号：US07672161B2

公开(公告)日：2010-03-02

申请号：US11742371

申请日：2007-04-30

申请人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

发明人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

IPC分类号： G11C11/03

CPC分类号： G11C11/5642

摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

摘要翻译： 介绍了便于从存储器访问数据的系统，方法和/或设备。 可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。 解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。 解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。 自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。 可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

公开(公告)号：US20080266945A1

公开(公告)日：2008-10-30

申请号：US11742371

申请日：2007-04-30

申请人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

发明人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

IPC分类号： G11C11/34

CPC分类号： G11C11/5642

摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

摘要翻译： 介绍了便于从存储器访问数据的系统，方法和/或设备。 可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。 解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。 解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。 自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。 可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

公开(公告)号：US20100205513A1

公开(公告)日：2010-08-12

申请号：US12368835

申请日：2009-02-10

申请人： Ping Hou ,  Eugen Gershon

发明人： Ping Hou ,  Eugen Gershon

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： G06F11/1008 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/6561

摘要： Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

摘要翻译： 公开了用于识别编码数据中的错误位的系统和方法。 作为识别错误位的一部分，访问从数据源提供并且包括数据和奇偶校验部分的编码数据。 基于编码数据，计算综合征，并且基于所计算的综合征，确定方程式。 确定等式的根，并且基于确定的等式的根，识别一个或多个错误位。 使用呈现根的二进制表示的电路来识别错误位。 错误位根据识别的错误位进行校正。

公开(公告)号：US20090106626A1

公开(公告)日：2009-04-23

申请号：US11877497

申请日：2007-10-23

申请人： Ping Hou ,  Eugen Gershon

发明人： Ping Hou ,  Eugen Gershon

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F21/73 ,  G06F11/1068 ,  G06F2221/2129 ,  H03M13/1111 ,  H03M13/1197

摘要： An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.

摘要翻译： 累积重复编码器可以便于编写写入存储器的数据，使得可以根据低密度奇偶校验（LDPC）码来生成奇偶校验数据。 原始数据和相关联的奇偶校验数据可以存储在存储器中。 在读取操作期间，解码器组件可以利用基于LDPC码的奇偶校验数据来促进从存储器读取的数据的解码。 解码器组件可以是迭代的，并且可以基于对读取数据的值的某些概率计算来提供一个或多个解码结果。 解码器组件可以分析解码结果并参考根据LDPC码构造的奇偶校验矩阵，以确定解码结果的准确性。 如果解码结果达到期望的精度，则解码结果可以是原始数据的表示，并且可以被提供为输出。

公开(公告)号：US08255777B2

公开(公告)日：2012-08-28

申请号：US12368835

申请日：2009-02-10

申请人： Ping Hou ,  Eugen Gershon

发明人： Ping Hou ,  Eugen Gershon

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/6561

摘要： Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

摘要翻译： 公开了用于识别编码数据中的错误位的系统和方法。 作为识别错误位的一部分，访问从数据源提供并且包括数据和奇偶校验部分的编码数据。 基于编码数据，计算综合征，并且基于所计算的综合征，确定方程式。 确定等式的根，并且基于确定的等式的根，识别一个或多个错误位。 使用呈现根的二进制表示的电路来识别错误位。 错误位根据识别的错误位进行校正。

公开(公告)号：US08301963B2

公开(公告)日：2012-10-30

申请号：US11877497

申请日：2007-10-23

申请人： Ping Hou ,  Eugen Gershon

发明人： Ping Hou ,  Eugen Gershon

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F21/73 ,  G06F11/1068 ,  G06F2221/2129 ,  H03M13/1111 ,  H03M13/1197

摘要： An accumulative repeat encoder facilitates encoding data written to memory, such that parity data is generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data is stored in memory. During a read operation, a decoder component utilizes the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component is iterative and provides one or more decoding results based on probabilities that symbols or bits comprising the data have correct values. The decoder component analyzes a decoding result and references a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result is determined to represent the original data and is provided as an output.

摘要翻译： 累积重复编码器有助于编码写入存储器的数据，使得根据低密度奇偶校验（LDPC）码产生奇偶校验数据。 原始数据和相关的奇偶校验数据存储在存储器中。 在读取操作期间，解码器组件利用基于LDPC码的奇偶校验数据来促进从存储器读取的数据的解码。 解码器组件是迭代的，并且基于包括数据的符号或位的正确值的概率提供一个或多个解码结果。 解码器组件分析解码结果并参考根据LDPC码构造的奇偶校验矩阵，以确定解码结果的准确性。 如果解码结果达到期望的精度，则确定解码结果以表示原始数据，并将其提供为输出。

公开(公告)号：US08261006B2

公开(公告)日：2012-09-04

申请号：US11960601

申请日：2007-12-19

申请人： Richard Chen ,  Ping Hou ,  Chih Hsueh

发明人： Richard Chen ,  Ping Hou ,  Chih Hsueh

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/214 ,  G06F2212/7203

摘要： Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

摘要翻译： 本文描述了用于提高闪存固态驱动装置的性能和可靠性的系统和方法。 闪存阵列组件存储数据。 存储器层次组件在主机和闪存阵列组件之间传输数据。 存储器层级组件包括耦合到合并缓冲器的一级（“L1”）高速缓存，闪存阵列组件和主机。 合并缓冲器耦合到闪存阵列组件。 L1缓存和合并缓冲区包括易失性存储器，并且主机耦合到合并缓冲区和闪存阵列组件。 存储器层级组件包括写入组件和读取组件。 写入组件将数据写入L1高速缓存，合并缓冲区或闪存阵列组件中的至少一个。 读取组件从L1高速缓存，合并缓冲器或闪存阵列组件中的至少一个读取数据。

公开(公告)号：US20100122146A1

公开(公告)日：2010-05-13

申请号：US12267017

申请日：2008-11-07

申请人： Hagop Nazarian ,  Ping Hou

发明人： Hagop Nazarian ,  Ping Hou

IPC分类号： G11C29/52 ,  G06F11/00

CPC分类号： G06F11/1072 ,  G11C2029/0411

摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

摘要翻译： 本文描述了提供电子存储器的单位和多位纠错。 作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。 可疑区域可以定义分布的潜在错误位。 如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。 通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

公开(公告)号：US20090164700A1

公开(公告)日：2009-06-25

申请号：US11960601

申请日：2007-12-19

申请人： Richard Chen ,  Ping Hou ,  Chih Hsueh

发明人： Richard Chen ,  Ping Hou ,  Chih Hsueh

IPC分类号： G06F12/02

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/214 ,  G06F2212/7203

摘要： Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

摘要翻译： 本文描述了用于提高闪存固态驱动装置的性能和可靠性的系统和方法。 闪存阵列组件存储数据。 存储器层次组件在主机和闪存阵列组件之间传输数据。 存储器层级组件包括耦合到合并缓冲器的一级（“L1”）高速缓存，闪存阵列组件和主机。 合并缓冲器耦合到闪存阵列组件。 L1缓存和合并缓冲区包括易失性存储器，并且主机耦合到合并缓冲区和闪存阵列组件。 存储器层级组件包括写入组件和读取组件。 写入组件将数据写入L1高速缓存，合并缓冲区或闪存阵列组件中的至少一个。 读取组件从L1高速缓存，合并缓冲器或闪存阵列组件中的至少一个读取数据。

公开(公告)号：US07445808B2

公开(公告)日：2008-11-04

申请号：US11320104

申请日：2005-12-28

申请人： Xuming Xiong ,  Venkat Selvamanickam ,  Ping Hou

发明人： Xuming Xiong ,  Venkat Selvamanickam ,  Ping Hou

IPC分类号： B05D5/12 ,  B05D3/00 ,  H01L39/24

CPC分类号： H01L39/2461 ,  Y10S505/74 ,  Y10T29/49014

摘要： A superconducting article and a method of making a superconducting article is described. The method of forming a superconducting article includes providing a substrate, forming a buffer layer to overlie the substrate, the buffer layer including a first buffer film deposited in the presence of an ion beam assist source and having a uniaxial crystal texture. The method further includes forming a superconducting layer to overlie the buffer layer.

摘要翻译： 描述超导制品和制造超导制品的方法。 形成超导体的方法包括提供衬底，形成覆盖在衬底上的缓冲层，缓冲层包括在离子束辅助源存在下沉积并具有单轴晶体结构的第一缓冲膜。 该方法还包括形成覆盖缓冲层的超导层。