公开(公告)号：US07320907B2

公开(公告)日：2008-01-22

申请号：US11000157

申请日：2004-11-29

申请人： Ping-Pang Hsieh ,  Ji-Fu Kung

发明人： Ping-Pang Hsieh ,  Ji-Fu Kung

IPC分类号： H01L21/84

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

摘要翻译： 描述了一种用于控制结处的晶格缺陷的方法，其用于伴随用于在衬底中形成结的离子注入步骤和随后的退火步骤。 在该方法中，进行额外的注入步骤以增加衬底中与接合部分之间的应力，使得在退火步骤中引起增强的再结晶以降低连接处的应力。 可以在用于形成结的离子注入步骤之前或之后执行额外的注入步骤。 还描述了用于形成CMOS器件的LDD或S / D区域的方法，其中在用于形成NMOS的LDD或S / D区域的离子注入步骤之前，之间或之后执行至少一个额外的注入步骤 和PMOS晶体管。

公开(公告)号：US20060115969A1

公开(公告)日：2006-06-01

申请号：US11000157

申请日：2004-11-29

申请人： Ping-Pang Hsieh ,  Ji-Fu Kung

发明人： Ping-Pang Hsieh ,  Ji-Fu Kung

IPC分类号： H01L21/425 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

摘要翻译： 描述了一种用于控制结处的晶格缺陷的方法，其用于伴随用于在衬底中形成结的离子注入步骤和随后的退火步骤。 在该方法中，进行额外的注入步骤以增加衬底中与接合部分之间的应力，使得在退火步骤中引起增强的再结晶以降低连接处的应力。 可以在用于形成结的离子注入步骤之前或之后执行额外的注入步骤。 还描述了用于形成CMOS器件的LDD或S / D区域的方法，其中在用于形成NMOS的LDD或S / D区域的离子注入步骤之前，之间或之后执行至少一个额外的注入步骤 和PMOS晶体管。

公开(公告)号：US07638400B2

公开(公告)日：2009-12-29

申请号：US11608927

申请日：2006-12-11

申请人： Ping-Pang Hsieh

发明人： Ping-Pang Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/6659

摘要： A method for forming a uniform doped region in a substrate having a non-uniform material layer thereon is provided. The non-uniform material layer is removed form the substrate. Thereafter, a treatment process is performed to form an offset material layer on a predetermined doped region of the substrate. Next, an ion implantation process is performed to form the uniform doped region in the predetermined doped region below the offset material layer.

摘要翻译： 提供了在其上具有不均匀材料层的衬底中形成均匀掺杂区域的方法。 从衬底去除不均匀的材料层。 此后，执行处理工艺以在衬底的预定掺杂区域上形成偏移材料层。 接下来，进行离子注入工艺以在偏移材料层下面的预定掺杂区域中形成均匀的掺杂区域。

公开(公告)号：US07126189B2

公开(公告)日：2006-10-24

申请号：US10820601

申请日：2004-04-07

申请人： Ping-Pang Hsieh

发明人： Ping-Pang Hsieh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26533 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：提供衬底; 在所述衬底上形成栅极结构，所述栅极结构包括在所述衬底上的栅极介电层和所述栅极介电层上的栅极导电层; 形成保形地覆盖所述基板和所述栅极结构的氧化物层; 形成覆盖所述氧化物层的电介质层; 去除所述电介质层的一部分以在所述栅极结构的侧壁上形成间隔物，所述间隔物和所述栅极结构之间的氧化物层作为氧化物间隔物; 进行氧等离子体处理工序，在氧化物层下方的基板中形成氧化硅层，氧化硅层和氧化物层为偏移氧化物层; 以及在栅极结构的两侧在衬底中形成源极/漏极区域。

公开(公告)号：US08980711B2

公开(公告)日：2015-03-17

申请号：US13484097

申请日：2012-05-30

申请人： Ping-Pang Hsieh ,  Kun-Tsang Chuang ,  Chia Hsing Huang

发明人： Ping-Pang Hsieh ,  Kun-Tsang Chuang ,  Chia Hsing Huang

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L21/28282 ,  H01L21/02164 ,  H01L21/02205 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833

摘要： A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate.

摘要翻译： 提供了一种用于制造存储器件的系统和方法。 优选实施例包括制造具有隧道层的闪存器件。 隧道层是通过将粘合剂引入电介质材料中而形成的，以便与另外将存在的悬挂键的键合并减少悬挂键的数量。 另外的实施方案包括开始形成隧道层而不用粘合剂，然后引入含有粘合剂的前体，并且还包括在与衬底相邻的隧穿层中形成的还原浓度区域。

公开(公告)号：US09263556B2

公开(公告)日：2016-02-16

申请号：US13538998

申请日：2012-06-29

申请人： Ping-Pang Hsieh ,  Chih-Ming Lee ,  Yu-Jen Chen

发明人： Ping-Pang Hsieh ,  Chih-Ming Lee ,  Yu-Jen Chen

IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L21/762 ,  H01L29/78 ,  H01L27/115

CPC分类号： H01L29/7883 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7853 ,  H01L29/7881

摘要： A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.

摘要翻译： 一种器件包括包括有源区的半导体衬底。 有源区包括第一侧壁。 隔离区域从半导体衬底的顶表面延伸到半导体衬底中。 隔离区域具有第二侧壁，其中第一侧壁的下部连接第二侧壁的下部以形成界面。 介电隔离件设置在第一侧壁的上部。 硅化物区域结束并与活性区域接触。 硅化物区域的侧壁接触电介质间隔物，并且电介质隔离物具有基本上比硅化物区域的顶表面低的顶表面。

公开(公告)号：US20140001529A1

公开(公告)日：2014-01-02

申请号：US13538998

申请日：2012-06-29

申请人： Ping-Pang Hsieh ,  Chih-Ming Lee ,  Yu-Jen Chen

发明人： Ping-Pang Hsieh ,  Chih-Ming Lee ,  Yu-Jen Chen

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7853 ,  H01L29/7881

摘要： A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region.

摘要翻译： 一种器件包括包括有源区的半导体衬底。 有源区包括第一侧壁。 隔离区域从半导体衬底的顶表面延伸到半导体衬底中。 隔离区域具有第二侧壁，其中第一侧壁的下部连接第二侧壁的下部以形成界面。 介电隔离件设置在第一侧壁的上部。 硅化物区域结束并与活性区域接触。 硅化物区域的侧壁接触电介质间隔物，并且电介质隔离物具有基本上比硅化物区域的顶表面低的顶表面。

公开(公告)号：US07157343B2

公开(公告)日：2007-01-02

申请号：US11078543

申请日：2005-03-11

申请人： Ping-Pang Hsieh

发明人： Ping-Pang Hsieh

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/26533 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：提供衬底; 在所述衬底上形成栅极结构，所述栅极结构包括在所述衬底上的栅极介电层和所述栅极介电层上的栅极导电层; 形成保形地覆盖所述基板和所述栅极结构的氧化物层; 形成覆盖所述氧化物层的电介质层; 去除所述电介质层的一部分以在所述栅极结构的侧壁上形成间隔物，所述间隔物和所述栅极结构之间的氧化物层作为氧化物间隔物; 进行氧等离子体处理工序，在氧化物层下方的基板中形成氧化硅层，氧化硅层和氧化物层为偏移氧化物层; 以及在栅极结构的两侧在衬底中形成源极/漏极区域。

公开(公告)号：US20130224943A1

公开(公告)日：2013-08-29

申请号：US13484097

申请日：2012-05-30

申请人： Ping-Pang Hsieh ,  Kun-Tsang Chuang ,  Chia Hsing Huang

发明人： Ping-Pang Hsieh ,  Kun-Tsang Chuang ,  Chia Hsing Huang

IPC分类号： H01L21/283

CPC分类号： H01L21/28282 ,  H01L21/02164 ,  H01L21/02205 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833

摘要： A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate.

公开(公告)号：US20070099387A1

公开(公告)日：2007-05-03

申请号：US11608927

申请日：2006-12-11

申请人： Ping-Pang Hsieh

发明人： Ping-Pang Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/6659

摘要： A method for forming a uniform doped region in a substrate having a non-uniform material layer thereon is provided. The non-uniform material layer is removed form the substrate. Thereafter, a treatment process is performed to form an offset material layer on a predetermined doped region of the substrate. Next, an ion implantation process is performed to form the uniform doped region in the predetermined doped region below the offset material layer.

摘要翻译： 提供了在其上具有不均匀材料层的衬底中形成均匀掺杂区域的方法。 从衬底去除不均匀的材料层。 此后，执行处理工艺以在衬底的预定掺杂区域上形成偏移材料层。 接下来，进行离子注入工艺以在偏移材料层下面的预定掺杂区域中形成均匀的掺杂区域。