-
公开(公告)号：US20190214367A1
公开(公告)日：2019-07-11
申请号：US15867613
申请日：2018-01-10
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Chi-An Wang , Hsien-Wen Hsu , Li-Chih Fang
IPC分类号： H01L25/065 , H01L25/00 , H01L23/28 , H01L23/538 , H01L23/552
CPC分类号： H01L25/0657 , H01L23/28 , H01L23/5384 , H01L23/552 , H01L25/50
摘要： A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
-
公开(公告)号：US20190244934A1
公开(公告)日：2019-08-08
申请号：US16386276
申请日：2019-04-17
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Chi-An Wang , Hsien-Wen Hsu
IPC分类号： H01L25/065 , H01L23/31 , H01L21/768 , H01L21/56 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/76805 , H01L23/3107 , H01L24/08 , H01L24/17 , H01L2224/02371
摘要： A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
-
3.发明授权公开(公告)号：US10354978B1
公开(公告)日：2019-07-16
申请号：US15867577
申请日：2018-01-10
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Chi-An Wang , Hsien-Wen Hsu
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00 , H01L21/56 , H01L21/768 , H01L21/78 , H01L25/00
摘要： A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
-
4.发明申请公开(公告)号：US20190214366A1
公开(公告)日：2019-07-11
申请号：US15867577
申请日：2018-01-10
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Chi-An Wang , Hsien-Wen Hsu
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L23/48 , H01L21/56 , H01L21/768 , H01L21/78
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/568 , H01L21/76898 , H01L21/78 , H01L23/481 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/96 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05024 , H01L2224/13026 , H01L2224/95001 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582
摘要： A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
-
公开(公告)号：US20170047295A1
公开(公告)日：2017-02-16
申请号：US15298234
申请日：2016-10-20
发明人： Yuan-Fu Lan , Hsien-Wen Hsu
IPC分类号： H01L23/00 , H05K1/18 , H01L23/498
CPC分类号： H01L23/562 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H05K1/18 , H05K2201/10204
摘要： A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.
摘要翻译： 载体衬底包括绝缘封装，第一导电图案，第二导电图案，至少一个第一虚设图案和至少一个第二虚设图案。 载体基板具有第一布局区域和第二布局区域。 第一导电图案和第一虚设图案位于第一布局区域中。 第二导电图案和第二虚设图案位于第二布局区域中。 第一和第二导电图案以及第一和第二虚设图案嵌入在绝缘封装中。 绝缘封装暴露了第一和第二导电图案以及第一和第二虚拟图案的顶表面。 第一虚设图案和第二虚设图案与第一导电图案和第二导电图案绝缘。 面向第二虚拟图案的第一伪图案的边缘轮廓是非线性的。
-
6.发明授权公开(公告)号：US10892250B2
公开(公告)日：2021-01-12
申请号：US16229562
申请日：2018-12-21
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Hsien-Wen Hsu
IPC分类号： H01L25/065 , H01L23/31 , H01L23/552 , H01L23/373 , H01L23/00 , H01L21/56
摘要： A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.
-
公开(公告)号：US10224254B2
公开(公告)日：2019-03-05
申请号：US15497219
申请日：2017-04-26
发明人： Ming-Chih Chen , Hsien-Wen Hsu , Yuan-Fu Lan , Hung-Hsin Hsu
IPC分类号： H01L23/043 , H01L23/06 , H01L23/31 , H01L21/82 , H01L23/498 , H01L23/00 , H01L23/48
摘要： A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.
-
公开(公告)号：US20180114782A1
公开(公告)日：2018-04-26
申请号：US15717953
申请日：2017-09-28
发明人： Chi-An Wang , Hung-Hsin Hsu , Yuan-Fu Lan , Hsien-Wen Hsu
IPC分类号： H01L25/10 , H01L23/498 , H01L23/49 , H01L21/56 , H01L25/00
摘要： A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.
-
公开(公告)号：US20170047277A1
公开(公告)日：2017-02-16
申请号：US15096293
申请日：2016-04-12
发明人： Yuan-Fu Lan , Hsien-Wen Hsu
IPC分类号： H01L23/498 , H05K3/26 , H05K1/02 , H05K3/00
CPC分类号： H05K1/0271 , H01L23/49894 , H01L23/528 , H01L23/5386
摘要： Provided is a semiconductor structure including a first die and a second die. The first die has a first conductive structure embedded in a dielectric layer. The second die has a second conductive structure embedded in the dielectric layer. A first interface is provided between the first conductive structure and the dielectric layer. A second interface is provided between the second conductive structure and the dielectric layer. A shape of the dielectric layer between the first interface and the second interface is a non-linear shape.
摘要翻译： 提供了包括第一管芯和第二管芯的半导体结构。 第一管芯具有嵌入电介质层中的第一导电结构。 第二管芯具有嵌入电介质层中的第二导电结构。 在第一导电结构和介电层之间提供第一界面。 在第二导电结构和电介质层之间提供第二接口。 第一界面和第二界面之间的介电层的形状是非线性形状。
-
公开(公告)号：US11024603B2
公开(公告)日：2021-06-01
申请号：US16386276
申请日：2019-04-17
发明人： Ming-Chih Chen , Hung-Hsin Hsu , Yuan-Fu Lan , Chi-An Wang , Hsien-Wen Hsu
IPC分类号： H01L25/065 , H01L21/76 , H01L23/31 , H01L21/768 , H01L23/00 , H01L21/56
摘要： A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.013 秒)
