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    Error signaling windows for phase-differential protocols
    1.
    发明授权
    Error signaling windows for phase-differential protocols 有权

    公开(公告)号：US11531608B2

    公开(公告)日：2022-12-20

    申请号：US17027541

    申请日：2020-09-21

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Lalan Jee Mishra

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/07 ,  G06F11/10 ,  G06F13/42

    Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

    I2C bus architecture using shared clock and dedicated data lines
    2.
    发明授权
    I2C bus architecture using shared clock and dedicated data lines 有权

    公开(公告)号：US11520729B2

    公开(公告)日：2022-12-06

    申请号：US17307842

    申请日：2021-05-04

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Sharon Graif ,  Lior Amarilio ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

    Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

    Fast termination of multilane single data rate transactions
    3.
    发明授权
    Fast termination of multilane single data rate transactions 有权

    公开(公告)号：US10684981B2

    公开(公告)日：2020-06-16

    申请号：US16381189

    申请日：2019-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Sharon Graif ,  Richard Dominic Wietfeldt

    IPC: G06F13/42

    Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

    Sensors global bus
    4.
    发明授权
    Sensors global bus 有权

    公开(公告)号：US10417172B2

    公开(公告)日：2019-09-17

    申请号：US15685783

    申请日：2017-08-24

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Douglas Wayne Hoffman

    IPC: G06F13/42

    Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.

    ACCELERATED I3C MASTER STOP
    6.
    发明申请
    ACCELERATED I3C MASTER STOP 审中-公开

    公开(公告)号：US20170371830A1

    公开(公告)日：2017-12-28

    申请号：US15633658

    申请日：2017-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron

    IPC: G06F13/42 ,  H04B1/58

    CPC classification number: G06F13/4282 ,  G06F2213/0016 ,  H04B1/58 ,  H04L7/00

    Abstract: Systems, methods, and apparatus for communication over to serial bus in accordance with an I3C protocol are described. A method performed at a master device includes causing a line driver to enter a high-impedance mode of operation, and receiving data from the serial bus. When a data line of the serial bus is in a high voltage state while a last bit of a data byte is being transmitted, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus while the last bit of the data byte is being transmitted. When a plurality of data bytes is sequentially transmitted with last bits that cause a low voltage state, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus after the last bit of the data byte is being transmitted

    SYSTEM AND METHODS OF REDUCING ENERGY CONSUMPTION BY SYNCHRONIZING SENSORS
    7.
    发明申请
    SYSTEM AND METHODS OF REDUCING ENERGY CONSUMPTION BY SYNCHRONIZING SENSORS 审中-公开
    通过同步传感器降低能源消耗的系统和方法

    公开(公告)号：US20160370845A1

    公开(公告)日：2016-12-22

    申请号：US15251757

    申请日：2016-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Puig ,  Justin Black ,  Rashmi Kulkarni

    IPC: G06F1/32 ,  G06F1/08 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G01D21/00 ,  G06F1/14 ,  G06F1/329 ,  Y02D10/24

    Abstract: Disclosed aspects relate to methods and apparatus for correcting a first sensor clock of a first sensor. The disclosed methods and apparatus effectuate receiving first and seconds signals in a sensor from a processor at known different times related to the timing of the processor clock. Based on the measured time interval between the times of the first and second signals as determined by the sensor, a clock correction factor may be determined in the sensor for correcting the timing of the sensor clock to be synchronized with the processor clock.

    Abstract translation: 公开的方面涉及用于校正第一传感器的第一传感器时钟的方法和装置。 所公开的方法和装置实现在与处理器时钟的定时有关的已知不同时间处理器中从处理器接收传感器中的第一和第二信号。 基于由传感器确定的第一和第二信号的时间之间的测量时间间隔，可以在传感器中确定时钟校正因子，用于校正要与处理器时钟同步的传感器时钟的定时。

    Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options
    8.
    发明授权
    Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options 有权

    公开(公告)号：US11847087B2

    公开(公告)日：2023-12-19

    申请号：US17477250

    申请日：2021-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F13/32 ,  G06F13/38

    CPC classification number: G06F13/4282 ,  G06F13/32 ,  G06F13/387

    Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

    SYSTEMS AND METHODS FOR CHIP OPERATION USING SERIAL PERIPHERAL INTERFACE (SPI) WITH REDUCED PIN OPTIONS
    9.
    发明申请
    SYSTEMS AND METHODS FOR CHIP OPERATION USING SERIAL PERIPHERAL INTERFACE (SPI) WITH REDUCED PIN OPTIONS 有权

    公开(公告)号：US20230083877A1

    公开(公告)日：2023-03-16

    申请号：US17477250

    申请日：2021-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F13/38 ,  G06F13/32

    Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

    Multilane heterogeneous serial bus
    10.
    发明授权
    Multilane heterogeneous serial bus 有权

    公开(公告)号：US10579581B2

    公开(公告)日：2020-03-03

    申请号：US16204401

    申请日：2018-11-29

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/42

    Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.

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