公开(公告)号：US20140306735A1

公开(公告)日：2014-10-16

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。

公开(公告)号：US11823962B2

公开(公告)日：2023-11-21

申请号：US17180652

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

IPC: H01L21/66 ,  G06F30/398

CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

公开(公告)号：US09673786B2

公开(公告)日：2017-06-06

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/02 ,  H03K3/289 ,  H03K19/00 ,  H03K3/012 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.