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    Low leakage retention register tray
    1.
    发明授权
    Low leakage retention register tray 有权
    低泄漏保持定位托盘

    公开(公告)号：US09178496B2

    公开(公告)日：2015-11-03

    申请号：US14605805

    申请日：2015-01-26

    Applicant: QUALCOMM, Incorporated

    Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

    IPC: H03K3/356 ,  H03K3/012 ,  H03K3/57 ,  H03K19/00 ,  G06F1/32

    CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

    Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

    LOW LEAKAGE RETENTION REGISTER TRAY
    2.
    发明申请
    LOW LEAKAGE RETENTION REGISTER TRAY 有权
    低漏电保持寄存器托盘

    公开(公告)号：US20150130524A1

    公开(公告)日：2015-05-14

    申请号：US14605805

    申请日：2015-01-26

    Applicant: QUALCOMM, Incorporated

    Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

    IPC: H03K3/012 ,  H03K19/00

    CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

    Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

    Shared-diffusion standard cell architecture
    3.
    发明授权
    Shared-diffusion standard cell architecture 有权
    共享扩散标准单元架构

    公开(公告)号：US08836040B2

    公开(公告)日：2014-09-16

    申请号：US13671114

    申请日：2012-11-07

    Applicant: QUALCOMM Incorporated

    Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/118 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

    Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

    Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域的上方，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

    LOW LEAKAGE RETENTION REGISTER TRAY
    5.
    发明申请
    LOW LEAKAGE RETENTION REGISTER TRAY 有权
    低漏电保持寄存器托盘

    公开(公告)号：US20140253197A1

    公开(公告)日：2014-09-11

    申请号：US13787666

    申请日：2013-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

    IPC: H03K3/012 ,  H03K3/57

    CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

    Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

    SHARED-DIFFUSION STANDARD CELL ARCHITECTURE
    6.
    发明申请
    SHARED-DIFFUSION STANDARD CELL ARCHITECTURE 有权
    共享扩展标准细胞结构

    公开(公告)号：US20140124868A1

    公开(公告)日：2014-05-08

    申请号：US13671114

    申请日：2012-11-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

    IPC: H01L27/092 ,  H01L29/66

    CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

    Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

    Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

    FLIP-FLOP WITH REDUCED RETENTION VOLTAGE
    10.
    发明申请
    FLIP-FLOP WITH REDUCED RETENTION VOLTAGE 有权
    FLIP-FLOP具有降低的保持电压

    公开(公告)号：US20140306735A1

    公开(公告)日：2014-10-16

    申请号：US13862015

    申请日：2013-04-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

    Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

    Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。

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