公开(公告)号：US09053773B2

公开(公告)日：2015-06-09

申请号：US14025741

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  Sachin Bapat ,  Sakthivel Packirisamy

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/08 ,  G11C8/16 ,  G11C8/00 ,  G11C8/12 ,  G11C8/18 ,  G11C29/00 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/18 ,  G11C29/818 ,  G11C2207/108 ,  Y10T29/49117

Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Abstract translation: 公开了一种具有存储器件的集成电路元件; P型半导体区域，包括耦合到存储器件的第一存储器端口电路的第一半导体器件，并且被配置为当第一半导体器件被激活时能够访问存储器件; N型半导体区域，包括耦合到所述存储器件的第二存储器端口电路的第二半导体器件，并且被配置为当所述第二半导体器件被激活时能够访问所述存储器件; 以及分布在P型和N型半导体区域上的多条信号线，包括耦合以允许第一半导体器件被激活的第一存储器端口选择线; 耦合以允许第二半导体器件被激活的第二存储器端口选择线; 以及设置在第一存储器端口选择线和第二存储器端口选择线之间的时钟信号线。

公开(公告)号：US09673786B2

公开(公告)日：2017-06-06

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/02 ,  H03K3/289 ,  H03K19/00 ,  H03K3/012 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

公开(公告)号：US20140306735A1

公开(公告)日：2014-10-16

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。