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1.发明授权Apparatus and method for controlling power supplied to circuits based on time delay to produce data 有权基于时间延迟来控制提供给电路的功率以产生数据的装置和方法公开(公告)号：US09052725B1
公开(公告)日：2015-06-09
申请号：US14082077
申请日：2013-11-15
Applicant: QUALCOMM Incorporated
Inventor： Hui William Song , Mohamed Hassan Abu-Rahma , Esin Terizioglu
CPC classification number: G05F5/00 , G06F1/3203 , G06F1/3206 , G06F1/3296 , Y02D10/172
Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.
Abstract translation: 一种用于基于诸如与生成数据相关联的时间延迟等性能来控制提供给数据生成电路的电力的装置和方法。 该装置包括：多个数据产生电路，被配置为响应于第一信号在相应的输出端产生数据; 多个定时电路，被配置为产生与在所述数据生成之间产生数据的所述第一信号与所述数据产生电路的各个输出端的数据出现之间的时间延迟有关的多个第二信号; 电源电路，被配置为产生用于向所述数据产生电路供电的电压; 功率控制器，被配置为基于所述多个第二信号来控制由所述电源电路产生的电压; 以及串行数据传送电路，被配置为将来自各个定时电路的多个第二信号串行传送到功率控制器。
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公开(公告)号：US20150077279A1
公开(公告)日：2015-03-19
申请号：US14029699
申请日：2013-09-17
Applicant: QUALCOMM Incorporated
Inventor： Hui William Song , Mohamed Hassan Abu-Rahma
IPC: H03M1/12
CPC classification number: G04F10/005 , H03H11/265 , H03K5/135 , H03L7/0814 , H03M1/00 , H03M1/12 , H03M2201/4233 , H04M1/505
Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.
Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。
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3.发明申请公开(公告)号：US20150137879A1
公开(公告)日：2015-05-21
申请号：US14082077
申请日：2013-11-15
Applicant: QUALCOMM Incorporated
Inventor： Hui William Song , Mohamed Hassan Abu-Rahma , Esin Terizioglu
IPC: G05F5/00
CPC classification number: G05F5/00 , G06F1/3203 , G06F1/3206 , G06F1/3296 , Y02D10/172
Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.
Abstract translation: 一种用于基于诸如与生成数据相关联的时间延迟等性能来控制提供给数据生成电路的电力的装置和方法。 该装置包括：多个数据产生电路，被配置为响应于第一信号在相应的输出端产生数据; 多个定时电路，被配置为产生与在所述数据生成之间产生数据的所述第一信号与所述数据产生电路的各个输出端的数据出现之间的时间延迟有关的多个第二信号; 电源电路，被配置为产生用于向所述数据产生电路供电的电压; 功率控制器，被配置为基于所述多个第二信号来控制由所述电源电路产生的电压; 以及串行数据传送电路，被配置为将来自各个定时电路的多个第二信号串行传送到功率控制器。
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公开(公告)号：US20140247652A1
公开(公告)日：2014-09-04
申请号：US13781759
申请日：2013-03-01
Applicant: QUALCOMM INCORPORATED
Inventor： Peng Jin , Mohamed Hassan Abu-Rahma , Fahad Ahmed , Jaeyoon Kim
CPC classification number: G05F3/02 , G11C5/14 , G11C7/00 , G11C11/419
Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.
Abstract translation: 公开了各种集成电路和操作集成电路的方法。 集成电路可以包括具有由集成电路制造期间的工艺变化而产生的一个或多个电参数的电路，以及被配置为向电路供应电压以为电路供电的电压源，其中电压源还被配置为 根据一个或多个电气参数调整电压。
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公开(公告)号：US09698267B2
公开(公告)日：2017-07-04
申请号：US14320897
申请日：2014-07-01
Applicant: QUALCOMM Incorporated
Inventor： Stanley Seungchul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
IPC: H01L29/786 , H01L29/78 , H01L27/108 , H01L29/66 , G11C11/40
CPC classification number: H01L29/785 , G11C11/40 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/7831 , H01L29/7841 , H01L29/7855 , H01L29/78648
Abstract: A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.
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Patent Agency Ranking
公开(公告)号：US20140269018A1
公开(公告)日：2014-09-18
申请号：US13799532
申请日：2013-03-13
Applicant: QUALCOMM INCORPORATED
Inventor： Peng Jin , Mohamed Hassan Abu-Rahma , Fahad Ahmed
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148
Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.
Abstract translation: 写辅助存储器包括预充电辅助电路，其辅助在写辅助之后的位线复用组的存储器单元中的存取单元的电源引线上的电源电压的预充电 通过将来自电源引线的电荷耦合在位线复用组的存储器单元中的剩余的非存取存储器单元的周期。
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公开(公告)号：US09092013B2
公开(公告)日：2015-07-28
申请号：US14029699
申请日：2013-09-17
Applicant: QUALCOMM Incorporated
Inventor： Hui William Song , Mohamed Hassan Abu-Rahma
CPC classification number: G04F10/005 , H03H11/265 , H03K5/135 , H03L7/0814 , H03M1/00 , H03M1/12 , H03M2201/4233 , H04M1/505
Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.
Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。
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公开(公告)号：US08976574B2
公开(公告)日：2015-03-10
申请号：US13799408
申请日：2013-03-13
Applicant: QUALCOMM Incorporated
Inventor： Fahad Ahmed , Mohamed Hassan Abu-Rahma , Peng Jin
CPC classification number: H01L22/34 , G11C11/41 , G11C29/24 , G11C29/50 , G11C2029/0403 , G11C2029/5006
Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.
Abstract translation: 公开了一种集成电路。 集成电路包括布置成存储数据的多个比特单元。 集成电路还包括被配置为生成用于确定位单元是否在过程角操作的输出的传感器。 传感器包括与位单元相同的电路。
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公开(公告)号：US20140306735A1
公开(公告)日：2014-10-16
申请号：US13862015
申请日：2013-04-12
Applicant: QUALCOMM INCORPORATED
Inventor： Seid Hadi Rasouli , Animesh Datta , Jay Madhukar Shah , Martin Saint-Laurent , Peeyush Kumar Parkar , Sachin Bapat , Ramaprasath Vilangudipitchai , Mohamed Hassan Abu-Rahma , Prayag Bhanubhai Patel
IPC: H03K3/012
CPC classification number: H03K3/012 , H03K3/356008 , H03K3/35625
Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。
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公开(公告)号：US09673786B2
公开(公告)日：2017-06-06
申请号：US13862015
申请日：2013-04-12
Applicant: QUALCOMM Incorporated
Inventor： Seid Hadi Rasouli , Animesh Datta , Jay Madhukar Shah , Martin Saint-Laurent , Peeyush Kumar Parkar , Sachin Bapat , Ramaprasath Vilangudipitchai , Mohamed Hassan Abu-Rahma , Prayag Bhanubhai Patel
CPC classification number: H03K3/012 , H03K3/356008 , H03K3/35625
Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
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