公开(公告)号：US20140247652A1

公开(公告)日：2014-09-04

申请号：US13781759

申请日：2013-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： Peng Jin ,  Mohamed Hassan Abu-Rahma ,  Fahad Ahmed ,  Jaeyoon Kim

IPC: G05F3/02 ,  G11C7/00

CPC classification number: G05F3/02 ,  G11C5/14 ,  G11C7/00 ,  G11C11/419

Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.

Abstract translation: 公开了各种集成电路和操作集成电路的方法。 集成电路可以包括具有由集成电路制造期间的工艺变化而产生的一个或多个电参数的电路，以及被配置为向电路供应电压以为电路供电的电压源，其中电压源还被配置为 根据一个或多个电气参数调整电压。

公开(公告)号：US20140269018A1

公开(公告)日：2014-09-18

申请号：US13799532

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Peng Jin ,  Mohamed Hassan Abu-Rahma ,  Fahad Ahmed

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148

Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

Abstract translation: 写辅助存储器包括预充电辅助电路，其辅助在写辅助之后的位线复用组的存储器单元中的存取单元的电源引线上的电源电压的预充电 通过将来自电源引线的电荷耦合在位线复用组的存储器单元中的剩余的非存取存储器单元的周期。

公开(公告)号：US09224453B2

公开(公告)日：2015-12-29

申请号：US13799532

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Peng Jin ,  Mohamed Hassan Abu-Rahma ,  Fahad Ahmed

IPC: G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148

Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

Abstract translation: 写辅助存储器包括预充电辅助电路，其辅助在写辅助之后的位线复用组的存储器单元中的存取单元的电源引线上的电源电压的预充电 通过将来自电源引线的电荷耦合到位线复用组的存储器单元中的剩余的非存取存储器单元。

公开(公告)号：US09019751B2

公开(公告)日：2015-04-28

申请号：US13781759

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Peng Jin ,  Mohamed Hassan Abu-Rahma ,  Fahad Ahmed ,  Jaeyoon Kim

IPC: G11C5/00 ,  G05F3/02 ,  G11C7/00 ,  G11C5/14 ,  G11C11/419

CPC classification number: G05F3/02 ,  G11C5/14 ,  G11C7/00 ,  G11C11/419

Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.

Abstract translation: 公开了各种集成电路和操作集成电路的方法。 集成电路可以包括具有由集成电路制造期间的工艺变化而产生的一个或多个电参数的电路，以及被配置为向电路供应电压以为电路供电的电压源，其中电压源还被配置为 根据一个或多个电气参数调整电压。

公开(公告)号：US20140269017A1

公开(公告)日：2014-09-18

申请号：US13799408

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Fahad Ahmed ,  Mohamed Hassan Abu-Rahma ,  Peng Jin

IPC: G11C29/04 ,  G11C11/417

CPC classification number: H01L22/34 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5006

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Abstract translation: 公开了一种集成电路。 集成电路包括布置成存储数据的多个比特单元。 集成电路还包括被配置为生成用于确定位单元是否在过程角操作的输出的传感器。 传感器包括与位单元相同的电路。

公开(公告)号：US20140198598A1

公开(公告)日：2014-07-17

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。

公开(公告)号：US08976574B2

公开(公告)日：2015-03-10

申请号：US13799408

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mohamed Hassan Abu-Rahma ,  Peng Jin

IPC: G11C11/00 ,  H01L21/66 ,  G11C29/50 ,  G11C29/24 ,  G11C11/41 ,  G11C29/04

CPC classification number: H01L22/34 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5006

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Abstract translation: 公开了一种集成电路。 集成电路包括布置成存储数据的多个比特单元。 集成电路还包括被配置为生成用于确定位单元是否在过程角操作的输出的传感器。 传感器包括与位单元相同的电路。

公开(公告)号：US08830780B2

公开(公告)日：2014-09-09

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。