公开(公告)号：US09916892B1

公开(公告)日：2018-03-13

申请号：US15448526

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Mukund Narasimhan ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.

公开(公告)号：US08976574B2

公开(公告)日：2015-03-10

申请号：US13799408

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mohamed Hassan Abu-Rahma ,  Peng Jin

IPC: G11C11/00 ,  H01L21/66 ,  G11C29/50 ,  G11C29/24 ,  G11C11/41 ,  G11C29/04

CPC classification number: H01L22/34 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5006

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Abstract translation: 公开了一种集成电路。 集成电路包括布置成存储数据的多个比特单元。 集成电路还包括被配置为生成用于确定位单元是否在过程角操作的输出的传感器。 传感器包括与位单元相同的电路。

公开(公告)号：US10713136B2

公开(公告)日：2020-07-14

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C29/00 ,  G06F11/20 ,  G11C29/44 ,  G11C8/12

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US09865337B1

公开(公告)日：2018-01-09

申请号：US15466749

申请日：2017-03-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mukund Narasimhan ,  Raghav Gupta ,  Pradeep Raj ,  Rahul Sahu ,  Po-Hung Chen ,  Chulmin Jung

IPC: G11C5/10 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/417

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

公开(公告)号：US09640231B1

公开(公告)日：2017-05-02

申请号：US15014830

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung

IPC: G11C7/00 ,  G11C7/06 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/222 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/002

Abstract: A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.

公开(公告)号：US09401201B1

公开(公告)日：2016-07-26

申请号：US14720383

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  David Li ,  Sei Seung Yoon

IPC: G11C11/41 ,  G11C11/419 ,  G11C5/14 ,  G11C11/413 ,  G11C16/10 ,  G11C16/06 ,  G11C7/12 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/413 ,  G11C13/0069 ,  G11C16/06 ,  G11C16/10

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract translation: 提供了一种用于操作存储器的存储器和方法。 存储器包括被配置为由第一电压源，位线和写入驱动器供电的存储器单元，配置为通过位线写入存储器单元，写入驱动器包括上拉电路，以将位线电压拉向 第二电压源，同时使用第一电压源来限制位线电压，第一和第二电压源处于不同的电压域。

公开(公告)号：US20190115091A1

公开(公告)日：2019-04-18

申请号：US15964050

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Greg Seok ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C29/44 ,  G11C29/10 ,  G11C29/18 ,  G11C29/16

Abstract: A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

公开(公告)号：US09997208B1

公开(公告)日：2018-06-12

申请号：US15473124

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

公开(公告)号：US09959912B2

公开(公告)日：2018-05-01

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/08 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

公开(公告)号：US09627041B1

公开(公告)日：2017-04-18

申请号：US15010385

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/417 ,  G11C11/418 ,  G11C29/12005 ,  G11C2029/1202

Abstract: A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.