公开(公告)号：US09881881B2

公开(公告)日：2018-01-30

申请号：US14809141

申请日：2015-07-24

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher N. Brindle ,  Anton Arriagada

IPC: H01L23/522 ,  H01L23/52 ,  H01L23/58 ,  H01L23/66 ,  H01L23/60 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/60 ,  H01L23/66

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

公开(公告)号：US09515139B2

公开(公告)日：2016-12-06

申请号：US14746398

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L29/0692 ,  H01L21/02365 ,  H01L21/2007 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/84 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

公开(公告)号：US11563456B2

公开(公告)日：2023-01-24

申请号：US17107952

申请日：2020-12-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel Filipovic ,  Jarred Moore ,  Maurice Adrianus De Jongh ,  Anton Arriagada

IPC: H04B1/16 ,  H03H7/38 ,  H04B1/18

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment circuit.

公开(公告)号：US20210083705A1

公开(公告)日：2021-03-18

申请号：US17107952

申请日：2020-12-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel Filipovic ,  Jarred Moore ,  Maurice Adrianus De Jongh ,  Anton Arriagada

IPC: H04B1/16 ,  H03H7/38 ,  H04B1/18

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment circuit.

公开(公告)号：US20200106467A1

公开(公告)日：2020-04-02

申请号：US16144670

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daniel Filipovic ,  Jarred Moore ,  Maurice Adrianus De Jongh ,  Anton Arriagada

IPC: H04B1/16 ,  H04B1/18 ,  H03H7/38

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment circuit.

公开(公告)号：US11683065B2

公开(公告)日：2023-06-20

申请号：US17150610

申请日：2021-01-15

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar Vedula ,  George Pete Imthurn ,  Anton Arriagada ,  Sinan Goktepeli

IPC: H04B1/44 ,  H03K17/687

CPC classification number: H04B1/44 ,  H03K17/6874

Abstract: A radio frequency (RF) switch includes switch transistors coupled in series. The RF switch includes a distributed gate bias network coupled to gate electrodes of the switch transistors. The RF switch also includes a distributed body bias network coupled to body electrodes of the switch transistors.

公开(公告)号：US10855320B2

公开(公告)日：2020-12-01

申请号：US16144670

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daniel Filipovic ,  Jarred Moore ,  Maurice Adrianus De Jongh ,  Anton Arriagada

IPC: H04B1/16 ,  H03H7/38 ,  H04B1/18

Abstract: An antenna system includes: a radiating element; a feed coupled to the radiating element at a first point on the radiating element and configured to convey energy to the radiating element; and a radiation-adjustment device coupled to the radiating element at a second point, configured to alter a radiation characteristic of the radiating element, and including: coarse-adjustment elements; an integrated-circuit chip including: switches, each coupled to a respective one of the coarse-adjustment elements where the coarse-adjustment elements are disposed external to the integrated-circuit chip; and a fine-adjustment circuit; the antenna system further including a controller communicatively coupled to the switches and to the fine-adjustment circuit, the controller configured to alter the radiation characteristic of the radiating element by selectively causing one or more of the switches to couple one or more of the coarse-adjustment elements to the radiating element, and by adjusting a value of the fine-adjustment circuit.

公开(公告)号：US09558951B2

公开(公告)日：2017-01-31

申请号：US14043764

申请日：2013-10-01

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Chris Brindle ,  Michael A. Stuber

IPC: H01L21/46 ,  H01L21/302 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/302 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/80001 ,  H01L2224/9202

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract translation: 集成电路芯片形成有电路层，阱富层和贯通半导体通孔。 陷阱富层形成在电路层上。 贯通半导体通孔也形成在电路层的上方。 在一些实施例中，电路层被包括在晶片中，并且阱富层和贯穿半导体通孔被包括在另一个晶片中。 在形成富集陷阱层和通过半导体通孔之后，两个晶片结合在一起。 另外，在一些实施例中，另一个晶片也可以结合到晶片上，该晶片包括陷阱富集层和贯穿半导体通路。 此外，在一些实施例中，可以在晶片中形成另外的电路层，其中包括阱富层和贯通半导体通路。

公开(公告)号：US20170025368A1

公开(公告)日：2017-01-26

申请号：US14809141

申请日：2015-07-24

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher N. Brindle ,  Anton Arriagada

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/66 ,  H01L23/60 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/585 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/60 ,  H01L23/66

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

Abstract translation: 多块半导体器件包括彼此以不同功率方式工作的第一块和第二块。 密封环围绕模具的周边，密封第一和第二块。 模具具有基板和绝缘层，密封环位于绝缘层上。 密封圈用作第一块的电源总线，但不是第二个块。 密封环和第一块电耦合到第一接地节点，第一接地节点与多块半导体器件中的其它接地节点在晶片级电隔离。 在一些实施例中，第二块位于模具的中心区域中，并且多个金属线将密封环电连接到第一块，金属线围绕半导体管芯的大部分周边均匀间隔开。