公开(公告)号：US20130302943A1

公开(公告)日：2013-11-14

申请号：US13945722

申请日：2013-07-18

Applicant: QUALCOMM Incorporated

Inventor： Arvind Chandrasekaran ,  Brian Matthew Henderson

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/525 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract translation: 可以制造堆叠集成电路（IC），其具有结合到双面第一层晶片的第二层晶片。 双面第一层晶片在晶片的正面和背面包括后端（BEOL）层。 第一层晶圆内的扩展触点连接前侧和后侧BEOL层。 延伸的接触延伸穿过第一层晶片的结。 第二层晶片通过延伸的触点耦合到第一层晶片的前侧。 附加触点将第一层晶片内的器件与前端BEOL层耦合。 当在堆叠的IC中使用双面晶片时，堆叠的IC的高度可能会降低。 堆叠的IC可以包括具有相同功能的晶片或具有不同功能的晶片。

公开(公告)号：US08912043B2

公开(公告)日：2014-12-16

申请号：US13945722

申请日：2013-07-18

Applicant: QUALCOMM Incorporated

Inventor： Arvind Chandrasekaran ,  Brian Matthew Henderson

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/50 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/525 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract translation: 可以制造堆叠集成电路（IC），其具有结合到双面第一层晶片的第二层晶片。 双面第一层晶片在晶片的正面和背面包括后端（BEOL）层。 第一层晶圆内的扩展触点连接前侧和后侧BEOL层。 延伸的接触延伸穿过第一层晶片的结。 第二层晶片通过延伸的触点耦合到第一层晶片的前侧。 附加触点将第一层晶片内的器件与前端BEOL层耦合。 当在堆叠的IC中使用双面晶片时，堆叠的IC的高度可能会降低。 堆叠的IC可以包括具有相同功能的晶片或具有不同功能的晶片。

公开(公告)号：US08513089B2

公开(公告)日：2013-08-20

申请号：US13681412

申请日：2012-11-19

Applicant: QUALCOMM Incorporated

Inventor： Arvind Chandrasekaran

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/302 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

公开(公告)号：US20130105559A1

公开(公告)日：2013-05-02

申请号：US13713822

申请日：2012-12-13

Applicant: Qualcomm Incorporated

Inventor： Arvind Chandrasekaran ,  Shiqun Gu ,  Christine S. Hau-Riege

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L21/76877 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump, Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Abstract translation: 微型接头中的电迁移会导致微胶囊中的空隙，从而降低了包含微型电池的集成电路的使用寿命。通过在焊料周围形成铜壳，电流寿命可能会增加。 一个微型块的铜壳接触第二个微型块的铜壳，以封闭微型接头的焊料。 铜壳允许通过微型块的更高的电流密度。 因此，可以以更小的间距制造较小的微胶片，而不会发生电迁移的故障。 此外，铜壳减少了衬底上的微型接头之间的短路或桥接。

公开(公告)号：US20130084686A1

公开(公告)日：2013-04-04

申请号：US13681412

申请日：2012-11-19

Applicant: Qualcomm Incorporated

Inventor： Arvind Chandrasekaran

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/302 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

Abstract translation: 半导体晶片在基板上具有半导体基板和薄膜。 衬底和/或膜具有至少一个蚀刻线，其产生不连续表面，其减小晶片中的残余应力。 当晶片薄时，减小半导体晶片中的残余应力减小晶片翘曲。 此外，可以使用隔离插塞来填充蚀刻线的一部分以防止层的短路。